PNaCl: Impl the other atomicrmw operations: nand, max, min, umax, and umin.

test/Transforms/NaCl/atomic/extra-rmw-operations.ll

Index: test/Transforms/NaCl/atomic/extra-rmw-operations.ll
diff --git a/test/Transforms/NaCl/atomic/extra-rmw-operations.ll b/test/Transforms/NaCl/atomic/extra-rmw-operations.ll
new file mode 100644
index 0000000000000000000000000000000000000000..f9fd7d867fdd48cabddcb0932028c5d6f591fd7e
--- /dev/null
+++ b/test/Transforms/NaCl/atomic/extra-rmw-operations.ll
@@ -0,0 +1,78 @@
+; RUN: opt -nacl-rewrite-atomics -S < %s | FileCheck %s
+
+; Check rewriting nand, max, min, umax, umin atomicrmw operations.
+
+target datalayout = "p:32:32:32"
+
+; We test nand with all types, but for brevity's sake we don't do so for the
+; other operations.
+define i8 @test_nand_i8(i8* %ptr, i8 %value) {
+  %res = atomicrmw nand i8* %ptr, i8 %value seq_cst
+  ret i8 %res
+}
+; CHECK-LABEL: @test_nand_i8
+; CHECK-NEXT:    %1 = load i8, i8* %ptr, align 1
+; CHECK-NEXT:    br label %atomicrmw.start
+
+; CHECK:       atomicrmw.start:
+; CHECK-NEXT:    %loaded = phi i8 [ %1, %0 ], [ %3, %atomicrmw.start ]
+; CHECK-NEXT:    %2 = and i8 %loaded, %value
+; CHECK-NEXT:    %new = xor i8 %2, -1
+; CHECK-NEXT:    %3 = call i8 @llvm.nacl.atomic.cmpxchg.i8(i8* %ptr, i8 %loaded, i8 %new, i32 6, i32 6)
+; CHECK-NEXT:    %success = icmp eq i8 %3, %loaded
+; CHECK-NEXT:    br i1 %success, label %atomicrmw.end, label %atomicrmw.start
+
+; CHECK:       atomicrmw.end:
+; CHECK-NEXT:    ret i8 %3
+
+
+
+define i16 @test_nand_i16(i16* %ptr, i16 %value) {
+  %res = atomicrmw nand i16* %ptr, i16 %value seq_cst
+  ret i16 %res
+}
+; CHECK-LABEL: @test_nand_i16
+; CHECK: @llvm.nacl.atomic.cmpxchg
+
+define i32 @test_nand_i32(i32* %ptr, i32 %value) {
+  %res = atomicrmw nand i32* %ptr, i32 %value seq_cst
+  ret i32 %res
+}
+; CHECK-LABEL: @test_nand_i32
+; CHECK: @llvm.nacl.atomic.cmpxchg
+
+define i64 @test_nand_i64(i64* %ptr, i64 %value) {
+  %res = atomicrmw nand i64* %ptr, i64 %value seq_cst
+  ret i64 %res
+}
+; CHECK-LABEL: @test_nand_i64
+; CHECK: @llvm.nacl.atomic.cmpxchg
+
+
+define i32 @test_max(i32* %ptr, i32 %value) {
+  %res = atomicrmw max i32* %ptr, i32 %value seq_cst
+  ret i32 %res
+}
+; CHECK-LABEL: @test_max
+; CHECK: @llvm.nacl.atomic.cmpxchg
+
+define i32 @test_min(i32* %ptr, i32 %value) {
+  %res = atomicrmw min i32* %ptr, i32 %value seq_cst
+  ret i32 %res
+}
+; CHECK-LABEL: @test_min
+; CHECK: @llvm.nacl.atomic.cmpxchg
+
+define i32 @test_umax(i32* %ptr, i32 %value) {
+  %res = atomicrmw umax i32* %ptr, i32 %value seq_cst
+  ret i32 %res
+}
+; CHECK-LABEL: @test_umax
+; CHECK: @llvm.nacl.atomic.cmpxchg
+
+define i32 @test_umin(i32* %ptr, i32 %value) {
+  %res = atomicrmw umin i32* %ptr, i32 %value seq_cst
+  ret i32 %res
+}
+; CHECK-LABEL: @test_umin
+; CHECK: @llvm.nacl.atomic.cmpxchg