PNaCl: Impl the other atomicrmw operations: nand, max, min, umax, and umin.

lib/Transforms/NaCl/RewriteAtomics.cpp

 //===- RewriteAtomics.cpp - Stabilize instructions used for concurrency ---===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This pass encodes atomics, volatiles and fences using NaCl intrinsics
 // instead of LLVM's regular IR instructions.
 //
 // All of the above are transformed into one of the
 // @llvm.nacl.atomic.* intrinsics.
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/Triple.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/InstVisitor.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/NaClAtomicIntrinsics.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/TargetRegistry.h"
 #include "llvm/Transforms/NaCl.h"
 #include <climits>
 #include <string>
 
 using namespace llvm;
 
 static cl::opt<bool> PNaClMemoryOrderSeqCstOnly(
     "pnacl-memory-order-seq-cst-only",
     cl::desc("PNaCl should upgrade all atomic memory orders to seq_cst"),
     cl::init(false));
@@ skipping 27 matching lines @@
         ModifiedModule(false) {}
   ~AtomicVisitor() {}
   bool modifiedModule() const { return ModifiedModule; }
 
   void visitLoadInst(LoadInst &I);
   void visitStoreInst(StoreInst &I);
   void visitAtomicCmpXchgInst(AtomicCmpXchgInst &I);
   void visitAtomicRMWInst(AtomicRMWInst &I);
   void visitFenceInst(FenceInst &I);
 
+  SmallVectorImpl<Function*>& getFunsWithExtraRMWOps() { return FunsWithExtraRMWOps; }
+
 private:
   Module &M;
   LLVMContext &C;
   const DataLayout TD;
   NaCl::AtomicIntrinsics AI;
   bool ModifiedModule;
 
+  /// These functions have atomic instructions which we expand with
+  /// -atomic-expand. We collect them here so we don't have to check every
+  /// instruction of every basicblock of every function in the module twice over
+  /// the coarse of the pass (under the assumption that atomic operations are
+  /// the expection rather than the rule).

[JF, 2015/07/23 22:44:38]

"exception"

+  SmallVector<Function*, 32> FunsWithExtraRMWOps;
+
   AtomicVisitor() = delete;
   AtomicVisitor(const AtomicVisitor &) = delete;
   AtomicVisitor &operator=(const AtomicVisitor &) = delete;
 
   /// Create an integer constant holding a NaCl::MemoryOrder that can be
   /// passed as an argument to one of the @llvm.nacl.atomic.*
   /// intrinsics. This function may strengthen the ordering initially
   /// specified by the instruction \p I for stability purpose.
   template <class Instruction>
   ConstantInt *freezeMemoryOrder(const Instruction &I, AtomicOrdering O) const;
@@ skipping 60 matching lines @@
 };
 }
 
 char RewriteAtomics::ID = 0;
 INITIALIZE_PASS(RewriteAtomics, "nacl-rewrite-atomics",
                 "rewrite atomics, volatiles and fences into stable "
                 "@llvm.nacl.atomics.* intrinsics",
                 false, false)
 
 bool RewriteAtomics::runOnModule(Module &M) {
+  // rewrite nand, (u)max, (u)min rmw atomics:
+  // First we need a target machine to appease its lordship:
+
+  // Get the target specific parser.
+  std::string Error;
+  Triple TheTriple = Triple("i686-none-nacl");
+  const Target *TheTarget = TargetRegistry::lookupTarget("", TheTriple,
+                                                         Error);
+  if (!TheTarget) {
+    errs() << "Looking up 'i686-none-nacl':" << ": " << Error;
+    report_fatal_error("Did you forget to initialize the x86 target?");
+  }
+
+  // Create the target machine:
+  std::unique_ptr<TargetMachine> Target(
+      TheTarget->createTargetMachine(TheTriple.getTriple(), "generic", "",
+                                     TargetOptions(), Reloc::Default,
+                                     CodeModel::Default, CodeGenOpt::Default));
+  assert(Target != nullptr);
+
+  std::unique_ptr<FunctionPass> AtomicRMWExpander
+    (createAtomicExpandPass(Target.get()));
+
+
   AtomicVisitor AV(M, *this);
   AV.visit(M);
-  return AV.modifiedModule();
+
+  bool Changed = AV.modifiedModule();
+
+  // Expand any leftover RMW atomics:
+  // This is done after because otherwise -atomic-expand will expand stuff we're
+  // capable of expanding, leaving us with less efficient code.
+  const size_t PrevLen = AV.getFunsWithExtraRMWOps().size();
+  for(auto *F : AV.getFunsWithExtraRMWOps()) {
+    const bool Expanded = AtomicRMWExpander->runOnFunction(*F);
+    (void)Expanded;
+    assert(Expanded);
+    // revisit the function, rewriting cmpxchg to the corresponding
+    // llvm.nacl.etc.etc.
+    AV.visit(*F);
+    Changed = true;
+  }
+  // assert that -atomic-expand didn't leave things we can't expand.
+  (void)PrevLen;
+  assert(PrevLen == AV.getFunsWithExtraRMWOps().size());
+
+  return Changed;
 }
 
 template <class Instruction>
 ConstantInt *AtomicVisitor::freezeMemoryOrder(const Instruction &I,
                                               AtomicOrdering O) const {
   NaCl::MemoryOrder AO = NaCl::MemoryOrderInvalid;
 
   // TODO Volatile load/store are promoted to sequentially consistent
   //      for now. We could do something weaker.
   if (const LoadInst *L = dyn_cast<LoadInst>(&I)) {
@@ skipping 162 matching lines @@
   replaceInstructionWithIntrinsicCall(I, Intrinsic, PH.OriginalPET, PH.PET,
                                       Args);
 }
 
 ///   %res = atomicrmw OP T* %ptr, T %val memory_order
 /// becomes:
 ///   %res = call T @llvm.nacl.atomic.rmw.i<size>(OP, %ptr, %val, memory_order)
 void AtomicVisitor::visitAtomicRMWInst(AtomicRMWInst &I) {
   NaCl::AtomicRMWOperation Op;
   switch (I.getOperation()) {
-  default: report_fatal_error("unsupported atomicrmw operation: " + ToStr(I));
+  default: {
+    // delegate to -atomic-expand
+    FunsWithExtraRMWOps.push_back(I.getParent()->getParent());
+    return;
+  }
   case AtomicRMWInst::Add: Op = NaCl::AtomicAdd; break;
   case AtomicRMWInst::Sub: Op = NaCl::AtomicSub; break;
   case AtomicRMWInst::And: Op = NaCl::AtomicAnd; break;
   case AtomicRMWInst::Or:  Op = NaCl::AtomicOr;  break;
   case AtomicRMWInst::Xor: Op = NaCl::AtomicXor; break;
   case AtomicRMWInst::Xchg: Op = NaCl::AtomicExchange; break;
   }
   PointerHelper<AtomicRMWInst> PH(*this, I);
   const NaCl::AtomicIntrinsics::AtomicIntrinsic *Intrinsic =
       findAtomicIntrinsic(I, Intrinsic::nacl_atomic_rmw, PH.PET);
@@ skipping 59 matching lines @@
                                         ArrayRef<Value *>());
   } else {
     const NaCl::AtomicIntrinsics::AtomicIntrinsic *Intrinsic =
         findAtomicIntrinsic(I, Intrinsic::nacl_atomic_fence, T);
     Value *Args[] = {freezeMemoryOrder(I, I.getOrdering())};
     replaceInstructionWithIntrinsicCall(I, Intrinsic, T, T, Args);
   }
 }
 
 ModulePass *llvm::createRewriteAtomicsPass() { return new RewriteAtomics(); }