PNaCl: Impl the other atomicrmw operations: nand, max, min, umax, and umin.

lib/Transforms/NaCl/RewriteAtomics.cpp

 //===- RewriteAtomics.cpp - Stabilize instructions used for concurrency ---===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This pass encodes atomics, volatiles and fences using NaCl intrinsics
 // instead of LLVM's regular IR instructions.
 //
 // All of the above are transformed into one of the
 // @llvm.nacl.atomic.* intrinsics.
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/Triple.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/InstVisitor.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/NaClAtomicIntrinsics.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/TargetRegistry.h"
 #include "llvm/Transforms/NaCl.h"
 #include <climits>
 #include <string>
 
 using namespace llvm;
 
 // TODO(jfb) Keep the default of this option to true for Chrome 42, and change
 //           it to false for Chrome 43. This allows the PNaCl translator to be
 //           updated before the SDK starts emitting atomic memory orders that
 //           the old translator rejected.
@@ skipping 121 matching lines @@
 };
 }
 
 char RewriteAtomics::ID = 0;
 INITIALIZE_PASS(RewriteAtomics, "nacl-rewrite-atomics",
                 "rewrite atomics, volatiles and fences into stable "
                 "@llvm.nacl.atomics.* intrinsics",
                 false, false)
 
 bool RewriteAtomics::runOnModule(Module &M) {
+  // rewrite nand, (u)max, (u)min rmw atomics:
+  // First we need a target machine to appease its lordship:
+
+  // Get the target specific parser.
+  std::string Error;
+  Triple TheTriple = Triple("i686-none-nacl");

[JF, 2015/02/16 21:09:01]

Does it need to be i686? Can you just have unknown or pnacl instead?

[Richard Diamond, 2015/02/16 23:36:31]

The other option is `x86_64`. Arm expands into some kind of target specific
llvm.arm.* combo (I didn't really examine it closely), and mips doesn't need to
expand anything (supported natively, I assume). AtomicExpandPass queries the
TargetMachine to determine what to expand/what to expand to/etc and without one
it won't do anything.

Of the three mentioned, only X86 expands those atomic RMWs to target independant
IR. (If this seems smelly to you, I 100% agree).

+  const Target *TheTarget = TargetRegistry::lookupTarget("", TheTriple,
+                                                         Error);
+  if (!TheTarget) {
+    errs() << "Looking up 'i686-none-nacl':" << ": " << Error;
+    report_fatal_error("Did you forget to initialize the x86 target?");
+  }
+
+  // Create the target machine:
+  std::unique_ptr<TargetMachine> target(
+      TheTarget->createTargetMachine(TheTriple.getTriple(), "generic", "i686",
+                                     TargetOptions(), Reloc::Default,
+                                     CodeModel::Default, CodeGenOpt::Default));
+
+  std::unique_ptr<FunctionPass> AtomicRMWExpander
+    (createAtomicExpandPass(target.get()));
+
+
   AtomicVisitor AV(M, *this);
   AV.visit(M);
-  return AV.modifiedModule();
+
+  bool Changed = AV.modifiedModule();
+
+  // Expand any leftover RMW atomics:
+  // This is done after because otherwise -atomic-expand will expand stuff we're
+  // capable of expanding, leaving us with less efficient code.
+  for(auto &F : M.functions()) {
+    if (AtomicRMWExpander->runOnFunction(F)) {
+      // revisit the function, rewriting cmpxchg to the corresponding
+      // llvm.nacl.etc.etc.
+      AV.visit(F);
+    }
+  }

[JF, 2015/02/16 21:09:01]

Could you invoke the -atomic-expand pass after this one, and then re-run this
one, from the pass registry instead of manually?

It also looks like the Changed flag won't be quite right (well, technically it
is because any -atomic-expand rewrite will trigger a rewrite atomic after, but
still...).

[Richard Diamond, 2015/02/16 23:36:31]

No, because it would force this kluge onto users. This hack requires a specific
TargetMachine to work.

Apropos to Changed flag: whoops, fixed.

+  return Changed;
 }
 
 template <class Instruction>
 ConstantInt *AtomicVisitor::freezeMemoryOrder(const Instruction &I,
                                               AtomicOrdering O) const {
   NaCl::MemoryOrder AO = NaCl::MemoryOrderInvalid;
 
   // TODO Volatile load/store are promoted to sequentially consistent
   //      for now. We could do something weaker.
   if (const LoadInst *L = dyn_cast<LoadInst>(&I)) {
@@ skipping 162 matching lines @@
   replaceInstructionWithIntrinsicCall(I, Intrinsic, PH.OriginalPET, PH.PET,
                                       Args);
 }
 
 ///   %res = atomicrmw OP T* %ptr, T %val memory_order
 /// becomes:
 ///   %res = call T @llvm.nacl.atomic.rmw.i<size>(OP, %ptr, %val, memory_order)
 void AtomicVisitor::visitAtomicRMWInst(AtomicRMWInst &I) {
   NaCl::AtomicRMWOperation Op;
   switch (I.getOperation()) {
-  default: report_fatal_error("unsupported atomicrmw operation: " + ToStr(I));
+  default: return; // -atomic-expand will handle it.

[JF, 2015/02/16 21:09:01]

It would be good to assert that the second pass of this never hits this case.

[Richard Diamond, 2015/02/16 23:36:31]

The second pass never reaches this. The other RMW ops are expanded to cmpxchg
instructions.

   case AtomicRMWInst::Add: Op = NaCl::AtomicAdd; break;
   case AtomicRMWInst::Sub: Op = NaCl::AtomicSub; break;
   case AtomicRMWInst::And: Op = NaCl::AtomicAnd; break;
   case AtomicRMWInst::Or:  Op = NaCl::AtomicOr;  break;
   case AtomicRMWInst::Xor: Op = NaCl::AtomicXor; break;
   case AtomicRMWInst::Xchg: Op = NaCl::AtomicExchange; break;
   }
   PointerHelper<AtomicRMWInst> PH(*this, I);
   const NaCl::AtomicIntrinsics::AtomicIntrinsic *Intrinsic =
       findAtomicIntrinsic(I, Intrinsic::nacl_atomic_rmw, PH.PET);
@@ skipping 59 matching lines @@
                                         ArrayRef<Value *>());
   } else {
     const NaCl::AtomicIntrinsics::AtomicIntrinsic *Intrinsic =
         findAtomicIntrinsic(I, Intrinsic::nacl_atomic_fence, T);
     Value *Args[] = {freezeMemoryOrder(I, I.getOrdering())};
     replaceInstructionWithIntrinsicCall(I, Intrinsic, T, T, Args);
   }
 }
 
 ModulePass *llvm::createRewriteAtomicsPass() { return new RewriteAtomics(); }