Convert a few lit tests that use "lc2i | llvm-mc | llvm-objdump" to use p2i.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
-; TODO(kschimpf) Find out why lc2i is needed.
-; RUN: %lc2i -i %s --args -O2 --verbose none \
+; RUN: %p2i -i %s --args -O2 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN:   | %iflc FileCheck %s
+; RUN:   | FileCheck %s
 ; RUN: %p2i -i %s --args -O2 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
 ; RUN:   | FileCheck --check-prefix=CHECKO2 %s
-; RUN: %lc2i -i %s --args -Om1 --verbose none \
+; RUN: %p2i -i %s --args -Om1 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN:   | %iflc FileCheck %s
+; RUN:   | FileCheck %s
 
 declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
 declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
 declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
 declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
 declare void @llvm.nacl.atomic.store.i8(i8, i8*, i32)
 declare void @llvm.nacl.atomic.store.i16(i16, i16*, i32)
 declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
 declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
 declare i8 @llvm.nacl.atomic.rmw.i8(i32, i8*, i8, i32)
@@ skipping 680 matching lines @@
 entry:
   %trunc_exp = trunc i32 %expected to i8
   %trunc_des = trunc i32 %desired to i8
   %ptr = inttoptr i32 %iptr to i8*
   %old = call i8 @llvm.nacl.atomic.cmpxchg.i8(i8* %ptr, i8 %trunc_exp,
                                               i8 %trunc_des, i32 6, i32 6)
   %old_ext = zext i8 %old to i32
   ret i32 %old_ext
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_8
-; CHECK: mov al, {{.*}}
+; CHECK: mov eax, {{.*}}
 ; Need to check that eax isn't used as the address register or the desired.
 ; since it is already used as the *expected* register.
 ; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], {{[^a]}}
+; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], {{[^a]}}l
 
 define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
 entry:
   %trunc_exp = trunc i32 %expected to i16
   %trunc_des = trunc i32 %desired to i16
   %ptr = inttoptr i32 %iptr to i16*
   %old = call i16 @llvm.nacl.atomic.cmpxchg.i16(i16* %ptr, i16 %trunc_exp,
                                                i16 %trunc_des, i32 6, i32 6)
   %old_ext = zext i16 %old to i32
   ret i32 %old_ext
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_16
-; CHECK: mov ax, {{.*}}
+; CHECK: mov eax, {{.*}}
 ; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], {{[^a]}}
+; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], {{[^a]}}x
 
 define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
                                                i32 %desired, i32 6, i32 6)
   ret i32 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_32
 ; CHECK: mov eax, {{.*}}
@@ skipping 30 matching lines @@
   ret void
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_store
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock
 ; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: mov {{.*}}, edx
-; CHECK: mov {{.*}}, eax
+; CHECK-DAG: mov {{.*}}, edx
+; CHECK-DAG: mov {{.*}}, eax
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 define i64 @test_atomic_cmpxchg_64_alloca(i32 %iptr, i64 %expected, i64 %desired) {
 entry:
   %alloca_ptr = alloca i8, i32 16, align 16
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                 i64 %desired, i32 6, i32 6)
   store i8 0, i8* %alloca_ptr, align 1
@@ skipping 114 matching lines @@
 
 not_lock_free:
   %z = add i32 %x, %y
   ret i32 %z
 }
 ; CHECK-LABEL: test_atomic_is_lock_free_can_dce
 ; CHECK: mov {{.*}}, 1
 ; CHECK: ret
 ; CHECK: add
 ; CHECK: ret