Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge)

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

Index: tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
index c16f7c0429d918694553d08895b1e73f4310b96a..fdd1d657356d61f05e8e0ea0ad542a28630e9c02 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
@@ -1,17 +1,11 @@
 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
 ; RUN:   | FileCheck %s
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN:   | FileCheck --check-prefix=CHECKO2 %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN:   | FileCheck --check-prefix=O2 %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
 ; RUN:   | FileCheck %s
 
 declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
@@ -53,8 +47,8 @@ entry:
   ret i32 %r
 }
 ; CHECK-LABEL: test_atomic_load_8
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, byte
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},BYTE
 
 define i32 @test_atomic_load_16(i32 %iptr) {
 entry:
@@ -64,8 +58,8 @@ entry:
   ret i32 %r
 }
 ; CHECK-LABEL: test_atomic_load_16
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, word
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},WORD
 
 define i32 @test_atomic_load_32(i32 %iptr) {
 entry:
@@ -74,8 +68,8 @@ entry:
   ret i32 %r
 }
 ; CHECK-LABEL: test_atomic_load_32
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},DWORD
 
 define i64 @test_atomic_load_64(i32 %iptr) {
 entry:
@@ -84,8 +78,8 @@ entry:
   ret i64 %r
 }
 ; CHECK-LABEL: test_atomic_load_64
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
 
 define i32 @test_atomic_load_32_with_arith(i32 %iptr) {
 entry:
@@ -98,13 +92,13 @@ next:
   ret i32 %r2
 }
 ; CHECK-LABEL: test_atomic_load_32_with_arith
-; CHECK: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
 ; The next instruction may be a separate load or folded into an add.
 ;
 ; In O2 mode, we know that the load and add are going to be fused.
-; CHECKO2-LABEL: test_atomic_load_32_with_arith
-; CHECKO2: mov {{.*}}, dword
-; CHECKO2: add {{.*}}, dword
+; O2-LABEL: test_atomic_load_32_with_arith
+; O2: mov {{.*}},DWORD
+; O2: add {{.*}},DWORD
 
 define i32 @test_atomic_load_32_ignored(i32 %iptr) {
 entry:
@@ -113,11 +107,11 @@ entry:
   ret i32 0
 }
 ; CHECK-LABEL: test_atomic_load_32_ignored
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, dword
-; CHECKO2-LABEL: test_atomic_load_32_ignored
-; CHECKO2: mov {{.*}}, dword
-; CHECKO2: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},DWORD
+; O2-LABEL: test_atomic_load_32_ignored
+; O2: mov {{.*}},DWORD
+; O2: mov {{.*}},DWORD
 
 define i64 @test_atomic_load_64_ignored(i32 %iptr) {
 entry:
@@ -126,8 +120,8 @@ entry:
   ret i64 0
 }
 ; CHECK-LABEL: test_atomic_load_64_ignored
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
 
 ;;; Store
 
@@ -139,7 +133,7 @@ entry:
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_8
-; CHECK: mov byte
+; CHECK: mov BYTE
 ; CHECK: mfence
 
 define void @test_atomic_store_16(i32 %iptr, i32 %v) {
@@ -150,7 +144,7 @@ entry:
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_16
-; CHECK: mov word
+; CHECK: mov WORD
 ; CHECK: mfence
 
 define void @test_atomic_store_32(i32 %iptr, i32 %v) {
@@ -160,7 +154,7 @@ entry:
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_32
-; CHECK: mov dword
+; CHECK: mov DWORD
 ; CHECK: mfence
 
 define void @test_atomic_store_64(i32 %iptr, i64 %v) {
@@ -170,8 +164,8 @@ entry:
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_64
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
 ; CHECK: mfence
 
 define void @test_atomic_store_64_const(i32 %iptr) {
@@ -181,10 +175,10 @@ entry:
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_64_const
-; CHECK: mov {{.*}}, 1942892530
-; CHECK: mov {{.*}}, 2874
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: mov {{.*}},0x73ce2ff2
+; CHECK: mov {{.*}},0xb3a
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
 ; CHECK: mfence
 
 
@@ -202,9 +196,8 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_add_8
-; CHECK: lock
-; CHECK-NEXT: xadd byte {{.*}}, [[REG:.*]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK: lock xadd BYTE {{.*}},[[REG:.*]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
 
 define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
 entry:
@@ -215,9 +208,8 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_add_16
-; CHECK: lock
-; CHECK-NEXT: xadd word {{.*}}, [[REG:.*]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK: lock xadd WORD {{.*}},[[REG:.*]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
 
 define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
 entry:
@@ -226,9 +218,8 @@ entry:
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_add_32
-; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG:.*]]
-; CHECK: mov {{.*}}, [[REG]]
+; CHECK: lock xadd DWORD {{.*}},[[REG:.*]]
+; CHECK: mov {{.*}},[[REG]]
 
 define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
 entry:
@@ -238,27 +229,23 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_add_64
 ; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
 ; RHS of add cannot be any of the e[abcd]x regs because they are
 ; clobbered in the loop, and the RHS needs to be remain live.
-; CHECK: add ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: adc ecx, {{.*e.[^x]}}
+; CHECK: add ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: adc ecx,{{.*e.[^x]}}
 ; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
 ; It can be esi, edi, or ebp though, for example (so we need to be careful
 ; about rejecting eb* and ed*.)
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne [[LABEL]]
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
-define void @use_ptr(i32 %iptr) {
-entry:
-  ret void
-}
+declare void @use_ptr(i32 %iptr)
 
 define i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
 entry:
@@ -284,9 +271,8 @@ entry:
 ; not esp, since that's the stack pointer and mucking with it will break
 ; the later use_ptr function call.
 ; That pretty much leaves esi, or edi as the only viable registers.
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{[ds]}}i]
-; CHECK: call use_ptr
+; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
+; CHECK: call {{.*}} R_{{.*}} use_ptr
 
 define i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
 entry:
@@ -297,8 +283,7 @@ entry:
 ; Technically this could use "lock add" instead of "lock xadd", if liveness
 ; tells us that the destination variable is dead.
 ; CHECK-LABEL: test_atomic_rmw_add_32_ignored
-; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG:.*]]
+; CHECK: lock xadd DWORD {{.*}},[[REG:.*]]
 
 ; Atomic RMW 64 needs to be expanded into its own loop.
 ; Make sure that works w/ non-trivial function bodies.
@@ -322,15 +307,14 @@ err:
 }
 ; CHECK-LABEL: test_atomic_rmw_add_64_loop
 ; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: add ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: adc ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
+; CHECK: add ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: adc ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
+; CHECK: jne [[LABEL]]
 
 ;; sub
 
@@ -344,9 +328,8 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_sub_8
 ; CHECK: neg [[REG:.*]]
-; CHECK: lock
-; CHECK-NEXT: xadd byte {{.*}}, [[REG]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK: lock xadd BYTE {{.*}},[[REG]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
 
 define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
 entry:
@@ -358,9 +341,8 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_sub_16
 ; CHECK: neg [[REG:.*]]
-; CHECK: lock
-; CHECK-NEXT: xadd word {{.*}}, [[REG]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK: lock xadd WORD {{.*}},[[REG]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
 
 define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
 entry:
@@ -370,9 +352,8 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_sub_32
 ; CHECK: neg [[REG:.*]]
-; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG]]
-; CHECK: mov {{.*}}, [[REG]]
+; CHECK: lock xadd DWORD {{.*}},[[REG]]
+; CHECK: mov {{.*}},[[REG]]
 
 define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
 entry:
@@ -382,15 +363,14 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_sub_64
 ; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: sub ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: sbb ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
+; CHECK: sub ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: sbb ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne [[LABEL]]
 
 
 define i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
@@ -402,8 +382,7 @@ entry:
 ; Could use "lock sub" instead of "neg; lock xadd"
 ; CHECK-LABEL: test_atomic_rmw_sub_32_ignored
 ; CHECK: neg [[REG:.*]]
-; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG]]
+; CHECK: lock xadd DWORD {{.*}},[[REG]]
 
 ;; or
 
@@ -416,13 +395,12 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_or_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
 ; Dest cannot be eax here, because eax is used for the old value. Also want
 ; to make sure that cmpxchg's source is the same register.
 ; CHECK: or [[REG:[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
 
 define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
 entry:
@@ -433,11 +411,10 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_or_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
 ; CHECK: or [[REG:[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
 
 define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
 entry:
@@ -446,11 +423,10 @@ entry:
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_or_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
 ; CHECK: or [[REG:e[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
 
 define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
 entry:
@@ -460,15 +436,14 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_or_64
 ; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: or ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: or ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
+; CHECK: or ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: or ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne [[LABEL]]
 
 define i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
 entry:
@@ -480,11 +455,10 @@ entry:
 ; Could just "lock or", if we inspect the liveness information first.
 ; Would also need a way to introduce "lock"'edness to binary
 ; operators without introducing overhead on the more common binary ops.
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
 ; CHECK: or [[REG:e[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
 
 ;; and
 
@@ -497,11 +471,10 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_and_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
 ; CHECK: and [[REG:[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
 
 define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
 entry:
@@ -512,11 +485,10 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_and_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
 ; CHECK: and
-; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}]
+; CHECK: jne
 
 define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
 entry:
@@ -525,11 +497,10 @@ entry:
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_and_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
 ; CHECK: and
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne
 
 define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
 entry:
@@ -539,15 +510,14 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_and_64
 ; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: and ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: and ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
+; CHECK: and ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: and ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne [[LABEL]]
 
 define i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
 entry:
@@ -557,11 +527,10 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_and_32_ignored
 ; Could just "lock and"
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
 ; CHECK: and
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne
 
 ;; xor
 
@@ -574,11 +543,10 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_xor_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
 ; CHECK: xor [[REG:[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
 
 define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
 entry:
@@ -589,11 +557,10 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_xor_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
 ; CHECK: xor
-; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}]
+; CHECK: jne
 
 
 define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
@@ -603,11 +570,10 @@ entry:
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_xor_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
 ; CHECK: xor
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne
 
 define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
 entry:
@@ -617,15 +583,14 @@ entry:
 }
 ; CHECK-LABEL: test_atomic_rmw_xor_64
 ; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: or ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: or ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: mov ebx,eax
+; CHECK: or ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: or ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne
 
 define i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
 entry:
@@ -634,11 +599,10 @@ entry:
   ret i32 %v
 }
 ; CHECK-LABEL: test_atomic_rmw_xor_32_ignored
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
 ; CHECK: xor
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne
 
 ;; exchange
 
@@ -651,7 +615,7 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_xchg_8
-; CHECK: xchg byte ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg BYTE PTR {{.*}},[[REG:.*]]
 
 define i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
 entry:
@@ -662,7 +626,7 @@ entry:
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_xchg_16
-; CHECK: xchg word ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg WORD PTR {{.*}},[[REG:.*]]
 
 define i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
 entry:
@@ -671,7 +635,7 @@ entry:
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_xchg_32
-; CHECK: xchg dword ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg DWORD PTR {{.*}},[[REG:.*]]
 
 define i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
 entry:
@@ -685,9 +649,8 @@ entry:
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [{{e.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg8b QWORD PTR [{{e.[^x]}}
+; CHECK: jne
 
 define i32 @test_atomic_rmw_xchg_32_ignored(i32 %iptr, i32 %v) {
 entry:
@@ -698,7 +661,7 @@ entry:
 ; In this case, ignoring the return value doesn't help. The xchg is
 ; used to do an atomic store.
 ; CHECK-LABEL: test_atomic_rmw_xchg_32_ignored
-; CHECK: xchg dword ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg DWORD PTR {{.*}},[[REG:.*]]
 
 ;;;; Cmpxchg
 
@@ -713,11 +676,10 @@ entry:
   ret i32 %old_ext
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_8
-; CHECK: mov eax, {{.*}}
+; CHECK: mov eax,{{.*}}
 ; Need to check that eax isn't used as the address register or the desired.
 ; since it is already used as the *expected* register.
-; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], {{[^a]}}l
+; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],{{[^a]}}l
 
 define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
 entry:
@@ -730,9 +692,8 @@ entry:
   ret i32 %old_ext
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_16
-; CHECK: mov eax, {{.*}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], {{[^a]}}x
+; CHECK: mov eax,{{.*}}
+; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],{{[^a]}}x
 
 define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
 entry:
@@ -742,9 +703,8 @@ entry:
   ret i32 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_32
-; CHECK: mov eax, {{.*}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; CHECK: mov eax,{{.*}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
 
 define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
 entry:
@@ -759,8 +719,7 @@ entry:
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 ; edx and eax are already the return registers, so they don't actually
 ; need to be reshuffled via movs. The next test stores the result
 ; somewhere, so in that case they do need to be mov'ed.
@@ -781,10 +740,9 @@ entry:
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK-DAG: mov {{.*}}, edx
-; CHECK-DAG: mov {{.*}}, eax
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK-DAG: mov {{.*}},edx
+; CHECK-DAG: mov {{.*}},eax
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
@@ -813,9 +771,8 @@ entry:
 ; not esp, since that's the stack pointer and mucking with it will break
 ; the later use_ptr function call.
 ; That pretty much leaves esi, or edi as the only viable registers.
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{[ds]}}i]
-; CHECK: call use_ptr
+; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
+; CHECK: call {{.*}} R_{{.*}} use_ptr
 
 define i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected, i32 %desired) {
 entry:
@@ -825,9 +782,8 @@ entry:
   ret i32 0
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_32_ignored
-; CHECK: mov eax, {{.*}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
+; CHECK: mov eax,{{.*}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
 
 define i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected, i64 %desired) {
 entry:
@@ -842,8 +798,7 @@ entry:
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 
 ;;;; Fence and is-lock-free.
 
@@ -871,7 +826,7 @@ entry:
   ret i32 %r
 }
 ; CHECK-LABEL: test_atomic_is_lock_free
-; CHECK: mov {{.*}}, 1
+; CHECK: mov {{.*}},0x1
 
 define i32 @test_not_lock_free(i32 %iptr) {
 entry:
@@ -881,7 +836,7 @@ entry:
   ret i32 %r
 }
 ; CHECK-LABEL: test_not_lock_free
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
 
 define i32 @test_atomic_is_lock_free_ignored(i32 %iptr) {
 entry:
@@ -890,11 +845,11 @@ entry:
   ret i32 0
 }
 ; CHECK-LABEL: test_atomic_is_lock_free_ignored
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
 ; This can get optimized out, because it's side-effect-free.
-; CHECKO2-LABEL: test_atomic_is_lock_free_ignored
-; CHECKO2-NOT: mov {{.*}}, 1
-; CHECKO2: mov {{.*}}, 0
+; O2-LABEL: test_atomic_is_lock_free_ignored
+; O2-NOT: mov {{.*}}, 1
+; O2: mov {{.*}},0x0
 
 ; TODO(jvoung): at some point we can take advantage of the
 ; fact that nacl.atomic.is.lock.free will resolve to a constant
@@ -915,7 +870,7 @@ not_lock_free:
   ret i32 %z
 }
 ; CHECK-LABEL: test_atomic_is_lock_free_can_dce
-; CHECK: mov {{.*}}, 1
+; CHECK: mov {{.*}},0x1
 ; CHECK: ret
 ; CHECK: add
 ; CHECK: ret