Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge)

tests_lit/llvm2ice_tests/vector-ops.ll

Index: tests_lit/llvm2ice_tests/vector-ops.ll
diff --git a/tests_lit/llvm2ice_tests/vector-ops.ll b/tests_lit/llvm2ice_tests/vector-ops.ll
index 0e093e96b95b8bc7c8898681a369c870d2bb5436..9a8d7872d6c8c5ea1bbdfacfd28718a08cde3775 100644
--- a/tests_lit/llvm2ice_tests/vector-ops.ll
+++ b/tests_lit/llvm2ice_tests/vector-ops.ll
@@ -1,18 +1,14 @@
 ; This checks support for insertelement and extractelement.
 
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN:   | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN:   | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 -mattr=sse4.1 --verbose \
+; RUN:   none \
 ; RUN:   | FileCheck --check-prefix=SSE41 %s
-; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -mattr=sse4.1 --verbose \
+; RUN:   none \
 ; RUN:   | FileCheck --check-prefix=SSE41 %s
 
 ; insertelement operations
@@ -21,10 +17,10 @@ define <4 x float> @insertelement_v4f32_0(<4 x float> %vec, float %elt) {
 entry:
   %res = insertelement <4 x float> %vec, float %elt, i32 0
   ret <4 x float> %res
-; CHECK-LABEL: insertelement_v4f32_0:
+; CHECK-LABEL: insertelement_v4f32_0
 ; CHECK: movss
 
-; SSE41-LABEL: insertelement_v4f32_0:
+; SSE41-LABEL: insertelement_v4f32_0
 ; SSE41: insertps {{.*}}, {{.*}}, 0
 }
 
@@ -32,11 +28,11 @@ define <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
 entry:
   %res = insertelement <4 x i32> %vec, i32 %elt, i32 0
   ret <4 x i32> %res
-; CHECK-LABEL: insertelement_v4i32_0:
+; CHECK-LABEL: insertelement_v4i32_0
 ; CHECK: movd xmm{{.*}},
 ; CHECK: movss
 
-; SSE41-LABEL: insertelement_v4i32_0:
+; SSE41-LABEL: insertelement_v4i32_0
 ; SSE41: pinsrd {{.*}}, {{.*}}, 0
 }
 
@@ -45,11 +41,11 @@ define <4 x float> @insertelement_v4f32_1(<4 x float> %vec, float %elt) {
 entry:
   %res = insertelement <4 x float> %vec, float %elt, i32 1
   ret <4 x float> %res
-; CHECK-LABEL: insertelement_v4f32_1:
+; CHECK-LABEL: insertelement_v4f32_1
 ; CHECK: shufps
 ; CHECK: shufps
 
-; SSE41-LABEL: insertelement_v4f32_1:
+; SSE41-LABEL: insertelement_v4f32_1
 ; SSE41: insertps {{.*}}, {{.*}}, 16
 }
 
@@ -57,11 +53,11 @@ define <4 x i32> @insertelement_v4i32_1(<4 x i32> %vec, i32 %elt) {
 entry:
   %res = insertelement <4 x i32> %vec, i32 %elt, i32 1
   ret <4 x i32> %res
-; CHECK-LABEL: insertelement_v4i32_1:
+; CHECK-LABEL: insertelement_v4i32_1
 ; CHECK: shufps
 ; CHECK: shufps
 
-; SSE41-LABEL: insertelement_v4i32_1:
+; SSE41-LABEL: insertelement_v4i32_1
 ; SSE41: pinsrd {{.*}}, {{.*}}, 1
 }
 
@@ -70,10 +66,10 @@ entry:
   %elt = trunc i32 %elt.arg to i16
   %res = insertelement <8 x i16> %vec, i16 %elt, i32 1
   ret <8 x i16> %res
-; CHECK-LABEL: insertelement_v8i16:
+; CHECK-LABEL: insertelement_v8i16
 ; CHECK: pinsrw
 
-; SSE41-LABEL: insertelement_v8i16:
+; SSE41-LABEL: insertelement_v8i16
 ; SSE41: pinsrw
 }
 
@@ -82,12 +78,12 @@ entry:
   %elt = trunc i32 %elt.arg to i8
   %res = insertelement <16 x i8> %vec, i8 %elt, i32 1
   ret <16 x i8> %res
-; CHECK-LABEL: insertelement_v16i8:
+; CHECK-LABEL: insertelement_v16i8
 ; CHECK: movups
 ; CHECK: lea
 ; CHECK: mov
 
-; SSE41-LABEL: insertelement_v16i8:
+; SSE41-LABEL: insertelement_v16i8
 ; SSE41: pinsrb
 }
 
@@ -96,10 +92,10 @@ entry:
   %elt = trunc i32 %elt.arg to i1
   %res = insertelement <4 x i1> %vec, i1 %elt, i32 0
   ret <4 x i1> %res
-; CHECK-LABEL: insertelement_v4i1_0:
+; CHECK-LABEL: insertelement_v4i1_0
 ; CHECK: movss
 
-; SSE41-LABEL: insertelement_v4i1_0:
+; SSE41-LABEL: insertelement_v4i1_0
 ; SSE41: pinsrd {{.*}}, {{.*}}, 0
 }
 
@@ -108,11 +104,11 @@ entry:
   %elt = trunc i32 %elt.arg to i1
   %res = insertelement <4 x i1> %vec, i1 %elt, i32 1
   ret <4 x i1> %res
-; CHECK-LABEL: insertelement_v4i1_1:
+; CHECK-LABEL: insertelement_v4i1_1
 ; CHECK: shufps
 ; CHECK: shufps
 
-; SSE41-LABEL: insertelement_v4i1_1:
+; SSE41-LABEL: insertelement_v4i1_1
 ; SSE41: pinsrd {{.*}}, {{.*}}, 1
 }
 
@@ -121,10 +117,10 @@ entry:
   %elt = trunc i32 %elt.arg to i1
   %res = insertelement <8 x i1> %vec, i1 %elt, i32 1
   ret <8 x i1> %res
-; CHECK-LABEL: insertelement_v8i1:
+; CHECK-LABEL: insertelement_v8i1
 ; CHECK: pinsrw
 
-; SSE41-LABEL: insertelement_v8i1:
+; SSE41-LABEL: insertelement_v8i1
 ; SSE41: pinsrw
 }
 
@@ -133,12 +129,12 @@ entry:
   %elt = trunc i32 %elt.arg to i1
   %res = insertelement <16 x i1> %vec, i1 %elt, i32 1
   ret <16 x i1> %res
-; CHECK-LABEL: insertelement_v16i1:
+; CHECK-LABEL: insertelement_v16i1
 ; CHECK: movups
 ; CHECK: lea
 ; CHECK: mov
 
-; SSE41-LABEL: insertelement_v16i1:
+; SSE41-LABEL: insertelement_v16i1
 ; SSE41: pinsrb
 }
 
@@ -148,10 +144,10 @@ define float @extractelement_v4f32(<4 x float> %vec) {
 entry:
   %res = extractelement <4 x float> %vec, i32 1
   ret float %res
-; CHECK-LABEL: extractelement_v4f32:
+; CHECK-LABEL: extractelement_v4f32
 ; CHECK: pshufd
 
-; SSE41-LABEL: extractelement_v4f32:
+; SSE41-LABEL: extractelement_v4f32
 ; SSE41: pshufd
 }
 
@@ -159,11 +155,11 @@ define i32 @extractelement_v4i32(<4 x i32> %vec) {
 entry:
   %res = extractelement <4 x i32> %vec, i32 1
   ret i32 %res
-; CHECK-LABEL: extractelement_v4i32:
+; CHECK-LABEL: extractelement_v4i32
 ; CHECK: pshufd
-; CHECK: movd {{.*}}, xmm
+; CHECK: movd {{.*}},xmm
 
-; SSE41-LABEL: extractelement_v4i32:
+; SSE41-LABEL: extractelement_v4i32
 ; SSE41: pextrd
 }
 
@@ -172,10 +168,10 @@ entry:
   %res = extractelement <8 x i16> %vec, i32 1
   %res.ext = zext i16 %res to i32
   ret i32 %res.ext
-; CHECK-LABEL: extractelement_v8i16:
+; CHECK-LABEL: extractelement_v8i16
 ; CHECK: pextrw
 
-; SSE41-LABEL: extractelement_v8i16:
+; SSE41-LABEL: extractelement_v8i16
 ; SSE41: pextrw
 }
 
@@ -184,12 +180,12 @@ entry:
   %res = extractelement <16 x i8> %vec, i32 1
   %res.ext = zext i8 %res to i32
   ret i32 %res.ext
-; CHECK-LABEL: extractelement_v16i8:
+; CHECK-LABEL: extractelement_v16i8
 ; CHECK: movups
 ; CHECK: lea
 ; CHECK: mov
 
-; SSE41-LABEL: extractelement_v16i8:
+; SSE41-LABEL: extractelement_v16i8
 ; SSE41: pextrb
 }
 
@@ -198,10 +194,10 @@ entry:
   %res = extractelement <4 x i1> %vec, i32 1
   %res.ext = zext i1 %res to i32
   ret i32 %res.ext
-; CHECK-LABEL: extractelement_v4i1:
+; CHECK-LABEL: extractelement_v4i1
 ; CHECK: pshufd
 
-; SSE41-LABEL: extractelement_v4i1:
+; SSE41-LABEL: extractelement_v4i1
 ; SSE41: pextrd
 }
 
@@ -210,10 +206,10 @@ entry:
   %res = extractelement <8 x i1> %vec, i32 1
   %res.ext = zext i1 %res to i32
   ret i32 %res.ext
-; CHECK-LABEL: extractelement_v8i1:
+; CHECK-LABEL: extractelement_v8i1
 ; CHECK: pextrw
 
-; SSE41-LABEL: extractelement_v8i1:
+; SSE41-LABEL: extractelement_v8i1
 ; SSE41: pextrw
 }
 
@@ -222,11 +218,11 @@ entry:
   %res = extractelement <16 x i1> %vec, i32 1
   %res.ext = zext i1 %res to i32
   ret i32 %res.ext
-; CHECK-LABEL: extractelement_v16i1:
+; CHECK-LABEL: extractelement_v16i1
 ; CHECK: movups
 ; CHECK: lea
 ; CHECK: mov
 
-; SSE41-LABEL: extractelement_v16i1:
+; SSE41-LABEL: extractelement_v16i1
 ; SSE41: pextrb
 }