tests_lit/llvm2ice_tests/vector-arith.ll - Issue 914263005: Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge)

Unified Diff: tests_lit/llvm2ice_tests/vector-arith.ll

Issue 914263005: Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Created 5 years, 10 months ago

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Index: tests_lit/llvm2ice_tests/vector-arith.ll

diff --git a/tests_lit/llvm2ice_tests/vector-arith.ll b/tests_lit/llvm2ice_tests/vector-arith.ll

index c7ef44f6c90f81c8892af202aa156c9ac6656d9c..d202ec3f035024a87400fbb17c1840ddad122820 100644

--- a/tests_lit/llvm2ice_tests/vector-arith.ll

+++ b/tests_lit/llvm2ice_tests/vector-arith.ll

@@ -1,25 +1,20 @@

; This test checks support for vector arithmetic.

-; RUN: %p2i -i %s -a -O2 --verbose none \

-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \

-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s

-; RUN: %p2i -i %s -a -Om1 --verbose none \

-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \

-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s

-; RUN: %p2i -i %s -a -O2 -mattr=sse4.1 --verbose none \

-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \

-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \

+; RUN: %p2i -i %s --assemble --disassemble -a -O2 --verbose none \

+; RUN: | FileCheck %s

+; RUN: %p2i -i %s --assemble --disassemble -a -Om1 --verbose none \

+; RUN: | FileCheck %s

+; RUN: %p2i -i %s --assemble --disassemble -a -O2 -mattr=sse4.1 --verbose none \

; RUN: | FileCheck --check-prefix=SSE41 %s

-; RUN: %p2i -i %s -a -Om1 -mattr=sse4.1 --verbose none \

-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \

-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \

+; RUN: %p2i -i %s --assemble --disassemble -a -Om1 -mattr=sse4.1 --verbose none \

+; RUN: \

jvoung (off chromium) 2015/02/13 23:37:23 Hmm...

; RUN: | FileCheck --check-prefix=SSE41 %s

define <4 x float> @test_fadd(<4 x float> %arg0, <4 x float> %arg1) {

entry:

%res = fadd <4 x float> %arg0, %arg1

ret <4 x float> %res

-; CHECK-LABEL: test_fadd:

+; CHECK-LABEL: test_fadd

; CHECK: addps

}

@@ -27,7 +22,7 @@ define <4 x float> @test_fsub(<4 x float> %arg0, <4 x float> %arg1) {

entry:

%res = fsub <4 x float> %arg0, %arg1

ret <4 x float> %res

-; CHECK-LABEL: test_fsub:

+; CHECK-LABEL: test_fsub

; CHECK: subps

}

@@ -35,7 +30,7 @@ define <4 x float> @test_fmul(<4 x float> %arg0, <4 x float> %arg1) {

entry:

%res = fmul <4 x float> %arg0, %arg1

ret <4 x float> %res

-; CHECK-LABEL: test_fmul:

+; CHECK-LABEL: test_fmul

; CHECK: mulps

}

@@ -43,7 +38,7 @@ define <4 x float> @test_fdiv(<4 x float> %arg0, <4 x float> %arg1) {

entry:

%res = fdiv <4 x float> %arg0, %arg1

ret <4 x float> %res

-; CHECK-LABEL: test_fdiv:

+; CHECK-LABEL: test_fdiv

; CHECK: divps

}

@@ -51,7 +46,7 @@ define <4 x float> @test_frem(<4 x float> %arg0, <4 x float> %arg1) {

entry:

%res = frem <4 x float> %arg0, %arg1

ret <4 x float> %res

-; CHECK-LABEL: test_frem:

+; CHECK-LABEL: test_frem

; CHECK: fmodf

@@ -62,7 +57,7 @@ define <16 x i8> @test_add_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = add <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_add_v16i8:

+; CHECK-LABEL: test_add_v16i8

; CHECK: paddb

}

@@ -70,7 +65,7 @@ define <16 x i8> @test_and_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = and <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_and_v16i8:

+; CHECK-LABEL: test_and_v16i8

; CHECK: pand

}

@@ -78,7 +73,7 @@ define <16 x i8> @test_or_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = or <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_or_v16i8:

+; CHECK-LABEL: test_or_v16i8

; CHECK: por

}

@@ -86,7 +81,7 @@ define <16 x i8> @test_xor_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = xor <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_xor_v16i8:

+; CHECK-LABEL: test_xor_v16i8

; CHECK: pxor

}

@@ -94,7 +89,7 @@ define <16 x i8> @test_sub_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = sub <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_sub_v16i8:

+; CHECK-LABEL: test_sub_v16i8

; CHECK: psubb

}

@@ -102,7 +97,7 @@ define <16 x i8> @test_mul_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = mul <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_mul_v16i8:

+; CHECK-LABEL: test_mul_v16i8

; CHECK: imul

@@ -125,7 +120,7 @@ define <16 x i8> @test_shl_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = shl <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_shl_v16i8:

+; CHECK-LABEL: test_shl_v16i8

; CHECK: shl

@@ -148,7 +143,7 @@ define <16 x i8> @test_lshr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = lshr <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_lshr_v16i8:

+; CHECK-LABEL: test_lshr_v16i8

; CHECK: shr

@@ -171,7 +166,7 @@ define <16 x i8> @test_ashr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = ashr <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_ashr_v16i8:

+; CHECK-LABEL: test_ashr_v16i8

; CHECK: sar

@@ -194,7 +189,7 @@ define <16 x i8> @test_udiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = udiv <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_udiv_v16i8:

+; CHECK-LABEL: test_udiv_v16i8

; CHECK: div

@@ -217,7 +212,7 @@ define <16 x i8> @test_sdiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = sdiv <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_sdiv_v16i8:

+; CHECK-LABEL: test_sdiv_v16i8

; CHECK: idiv

@@ -240,7 +235,7 @@ define <16 x i8> @test_urem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = urem <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_urem_v16i8:

+; CHECK-LABEL: test_urem_v16i8

; CHECK: div

@@ -263,7 +258,7 @@ define <16 x i8> @test_srem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {

entry:

%res = srem <16 x i8> %arg0, %arg1

ret <16 x i8> %res

-; CHECK-LABEL: test_srem_v16i8:

+; CHECK-LABEL: test_srem_v16i8

; CHECK: idiv

@@ -286,7 +281,7 @@ define <8 x i16> @test_add_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = add <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_add_v8i16:

+; CHECK-LABEL: test_add_v8i16

; CHECK: paddw

}

@@ -294,7 +289,7 @@ define <8 x i16> @test_and_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = and <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_and_v8i16:

+; CHECK-LABEL: test_and_v8i16

; CHECK: pand

}

@@ -302,7 +297,7 @@ define <8 x i16> @test_or_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = or <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_or_v8i16:

+; CHECK-LABEL: test_or_v8i16

; CHECK: por

}

@@ -310,7 +305,7 @@ define <8 x i16> @test_xor_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = xor <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_xor_v8i16:

+; CHECK-LABEL: test_xor_v8i16

; CHECK: pxor

}

@@ -318,7 +313,7 @@ define <8 x i16> @test_sub_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = sub <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_sub_v8i16:

+; CHECK-LABEL: test_sub_v8i16

; CHECK: psubw

}

@@ -326,7 +321,7 @@ define <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = mul <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_mul_v8i16:

+; CHECK-LABEL: test_mul_v8i16

; CHECK: pmullw

}

@@ -334,7 +329,7 @@ define <8 x i16> @test_shl_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = shl <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_shl_v8i16:

+; CHECK-LABEL: test_shl_v8i16

; CHECK: shl

@@ -349,7 +344,7 @@ define <8 x i16> @test_lshr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = lshr <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_lshr_v8i16:

+; CHECK-LABEL: test_lshr_v8i16

; CHECK: shr

@@ -364,7 +359,7 @@ define <8 x i16> @test_ashr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = ashr <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_ashr_v8i16:

+; CHECK-LABEL: test_ashr_v8i16

; CHECK: sar

@@ -379,7 +374,7 @@ define <8 x i16> @test_udiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = udiv <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_udiv_v8i16:

+; CHECK-LABEL: test_udiv_v8i16

; CHECK: div

@@ -394,7 +389,7 @@ define <8 x i16> @test_sdiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = sdiv <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_sdiv_v8i16:

+; CHECK-LABEL: test_sdiv_v8i16

; CHECK: idiv

@@ -409,7 +404,7 @@ define <8 x i16> @test_urem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = urem <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_urem_v8i16:

+; CHECK-LABEL: test_urem_v8i16

; CHECK: div

@@ -424,7 +419,7 @@ define <8 x i16> @test_srem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {

entry:

%res = srem <8 x i16> %arg0, %arg1

ret <8 x i16> %res

-; CHECK-LABEL: test_srem_v8i16:

+; CHECK-LABEL: test_srem_v8i16

; CHECK: idiv

@@ -439,7 +434,7 @@ define <4 x i32> @test_add_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = add <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_add_v4i32:

+; CHECK-LABEL: test_add_v4i32

; CHECK: paddd

}

@@ -447,7 +442,7 @@ define <4 x i32> @test_and_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = and <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_and_v4i32:

+; CHECK-LABEL: test_and_v4i32

; CHECK: pand

}

@@ -455,7 +450,7 @@ define <4 x i32> @test_or_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = or <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_or_v4i32:

+; CHECK-LABEL: test_or_v4i32

; CHECK: por

}

@@ -463,7 +458,7 @@ define <4 x i32> @test_xor_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = xor <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_xor_v4i32:

+; CHECK-LABEL: test_xor_v4i32

; CHECK: pxor

}

@@ -471,7 +466,7 @@ define <4 x i32> @test_sub_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = sub <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_sub_v4i32:

+; CHECK-LABEL: test_sub_v4i32

; CHECK: psubd

}

@@ -479,11 +474,11 @@ define <4 x i32> @test_mul_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = mul <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_mul_v4i32:

+; CHECK-LABEL: test_mul_v4i32

; CHECK: pmuludq

;

-; SSE41-LABEL: test_mul_v4i32:

+; SSE41-LABEL: test_mul_v4i32

; SSE41: pmulld

}

@@ -491,21 +486,21 @@ define <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = shl <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_shl_v4i32:

+; CHECK-LABEL: test_shl_v4i32

; CHECK: shl

; This line is to ensure that pmulld is generated in test_mul_v4i32 above.

-; SSE41-LABEL: test_shl_v4i32:

+; SSE41-LABEL: test_shl_v4i32

}

define <4 x i32> @test_lshr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = lshr <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_lshr_v4i32:

+; CHECK-LABEL: test_lshr_v4i32

; CHECK: shr

@@ -516,7 +511,7 @@ define <4 x i32> @test_ashr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = ashr <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_ashr_v4i32:

+; CHECK-LABEL: test_ashr_v4i32

; CHECK: sar

@@ -527,7 +522,7 @@ define <4 x i32> @test_udiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = udiv <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_udiv_v4i32:

+; CHECK-LABEL: test_udiv_v4i32

; CHECK: div

@@ -538,7 +533,7 @@ define <4 x i32> @test_sdiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = sdiv <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_sdiv_v4i32:

+; CHECK-LABEL: test_sdiv_v4i32

; CHECK: idiv

@@ -549,7 +544,7 @@ define <4 x i32> @test_urem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = urem <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_urem_v4i32:

+; CHECK-LABEL: test_urem_v4i32

; CHECK: div

@@ -560,7 +555,7 @@ define <4 x i32> @test_srem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {

entry:

%res = srem <4 x i32> %arg0, %arg1

ret <4 x i32> %res

-; CHECK-LABEL: test_srem_v4i32:

+; CHECK-LABEL: test_srem_v4i32

; CHECK: idiv