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Unified Diff: tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll

Issue 914263005: Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 10 months ago
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« tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll ('K') | « tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll ('k') | tests_lit/llvm2ice_tests/nop-insertion.ll » ('j') | tests_lit/llvm2ice_tests/vector-arith.ll » ('J')
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Index: tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
diff --git a/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
index 29e8def5c8d2817f5e2e6f101ee732321223dbb2..1883a1d42b1ab3514fdd42c70671570f386bc2d4 100644
--- a/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
@@ -1,26 +1,20 @@
; This tests the NaCl intrinsics not related to atomic operations.
-; RUN: %p2i -i %s --args -O2 --verbose none -sandbox \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none -sandbox \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none -sandbox \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none -sandbox \
+; RUN: | FileCheck %s
; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1
; share the same "CHECK" prefix). This separate run helps check that
; some code is optimized out.
-; RUN: %p2i -i %s --args -O2 --verbose none -sandbox \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none -sandbox \
; RUN: | FileCheck --check-prefix=CHECKO2REM %s
; Do O2 runs without -sandbox to make sure llvm.nacl.read.tp gets
; lowered to __nacl_read_tp instead of gs:[0x0].
; We also know that because it's O2, it'll have the O2REM optimizations.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck --check-prefix=CHECKO2UNSANDBOXEDREM %s
declare i8* @llvm.nacl.read.tp()
@@ -51,9 +45,9 @@ entry:
ret i32 %__1
}
; CHECK-LABEL: test_nacl_read_tp
-; CHECK: mov e{{.*}}, dword ptr gs:[0]
+; CHECK: mov e{{.*}},DWORD ptr gs:[0]
; CHECKO2REM-LABEL: test_nacl_read_tp
-; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
+; CHECKO2REM: mov e{{.*}}, DWORD PTR gs:[0]
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp
; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
@@ -75,11 +69,11 @@ entry:
ret i32 %v
}
; CHECK-LABEL: test_nacl_read_tp_more_addressing
-; CHECK: mov e{{.*}}, dword ptr gs:[0]
-; CHECK: mov e{{.*}}, dword ptr gs:[0]
+; CHECK: mov e{{.*}},DWORD ptr gs:[0]
+; CHECK: mov e{{.*}},DWORD ptr gs:[0]
; CHECKO2REM-LABEL: test_nacl_read_tp_more_addressing
-; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
-; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
+; CHECKO2REM: mov e{{.*}}, DWORD PTR gs:[0]
+; CHECKO2REM: mov e{{.*}}, DWORD PTR gs:[0]
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_more_addressing
; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
@@ -93,7 +87,7 @@ entry:
}
; Consider nacl.read.tp side-effect free, so it can be eliminated.
; CHECKO2REM-LABEL: test_nacl_read_tp_dead
-; CHECKO2REM-NOT: mov e{{.*}}, dword ptr gs:[0]
+; CHECKO2REM-NOT: mov e{{.*}}, DWORD PTR gs:[0]
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_dead
; CHECKO2UNSANDBOXEDREM-NOT: call __nacl_read_tp
@@ -106,7 +100,8 @@ entry:
ret void
}
; CHECK-LABEL: test_memcpy
-; CHECK: call memcpy
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} memcpy
; CHECKO2REM-LABEL: test_memcpy
; CHECKO2UNSANDBOXEDREM-LABEL: test_memcpy
@@ -121,7 +116,8 @@ entry:
ret void
}
; CHECK-LABEL: test_memcpy_const_len_align
-; CHECK: call memcpy
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} memcpy
define void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
entry:
@@ -132,7 +128,8 @@ entry:
ret void
}
; CHECK-LABEL: test_memmove
-; CHECK: call memmove
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} memmove
define void @test_memmove_const_len_align(i32 %iptr_dst, i32 %iptr_src) {
entry:
@@ -143,7 +140,8 @@ entry:
ret void
}
; CHECK-LABEL: test_memmove_const_len_align
-; CHECK: call memmove
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} memmove
define void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
entry:
@@ -155,7 +153,8 @@ entry:
}
; CHECK-LABEL: test_memset
; CHECK: movzx
-; CHECK: call memset
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} memset
define void @test_memset_const_len_align(i32 %iptr_dst, i32 %wide_val) {
entry:
@@ -167,7 +166,8 @@ entry:
}
; CHECK-LABEL: test_memset_const_len_align
; CHECK: movzx
-; CHECK: call memset
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} memset
define void @test_memset_const_val(i32 %iptr_dst, i32 %len) {
entry:
@@ -177,8 +177,9 @@ entry:
}
; CHECK-LABEL: test_memset_const_val
; Make sure the argument is legalized (can't movzx reg, 0).
-; CHECK: movzx {{.*}}, {{[^0]}}
-; CHECK: call memset
+; CHECK: movzx {{.*}},{{[^0]}}
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} memset
define i32 @test_setjmplongjmp(i32 %iptr_env) {
@@ -196,8 +197,10 @@ NonZero:
ret i32 1
}
; CHECK-LABEL: test_setjmplongjmp
-; CHECK: call setjmp
-; CHECK: call longjmp
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} setjmp
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} longjmp
; CHECKO2REM-LABEL: test_setjmplongjmp
; CHECKO2REM: call setjmp
; CHECKO2REM: call longjmp
@@ -224,7 +227,7 @@ entry:
; CHECK-LABEL: test_sqrt_float
; CHECK: sqrtss xmm{{.*}}
; CHECK: sqrtss xmm{{.*}}
-; CHECK: sqrtss xmm{{.*}}, dword ptr
+; CHECK: sqrtss xmm{{.*}}, DWORD PTR
define float @test_sqrt_float_mergeable_load(float %x, i32 %iptr) {
entry:
@@ -251,7 +254,7 @@ entry:
; CHECK-LABEL: test_sqrt_double
; CHECK: sqrtsd xmm{{.*}}
; CHECK: sqrtsd xmm{{.*}}
-; CHECK: sqrtsd xmm{{.*}}, qword ptr
+; CHECK: sqrtsd xmm{{.*}}, QWORD PTR
define double @test_sqrt_double_mergeable_load(double %x, i32 %iptr) {
entry:
@@ -326,8 +329,8 @@ entry:
; and avoid the need to do the cmovne and xor stuff to guarantee that
; the result is well-defined w/ input == 0.
; CHECK: bsr [[REG_TMP:e.*]], {{.*}}
-; CHECK: mov [[REG_RES:e.*]], 63
-; CHECK: cmovne [[REG_RES]], [[REG_TMP]]
+; CHECK: mov [[REG_RES:e.*]],63
+; CHECK: cmovne [[REG_RES]],[[REG_TMP]]
; CHECK: xor [[REG_RES]], 31
define i32 @test_ctlz_32_const() {
@@ -357,15 +360,15 @@ entry:
; CHECKO2REM-LABEL: test_ctlz_64
; CHECK-LABEL: test_ctlz_64
; CHECK: bsr [[REG_TMP1:e.*]], {{.*}}
-; CHECK: mov [[REG_RES1:e.*]], 63
-; CHECK: cmovne [[REG_RES1]], [[REG_TMP1]]
+; CHECK: mov [[REG_RES1:e.*]],63
+; CHECK: cmovne [[REG_RES1]],[[REG_TMP1]]
; CHECK: xor [[REG_RES1]], 31
; CHECK: add [[REG_RES1]], 32
; CHECK: bsr [[REG_RES2:e.*]], {{.*}}
; CHECK: xor [[REG_RES2]], 31
; CHECK: test [[REG_UPPER:.*]], [[REG_UPPER]]
-; CHECK: cmove [[REG_RES2]], [[REG_RES1]]
-; CHECK: mov {{.*}}, 0
+; CHECK: cmove [[REG_RES2]],[[REG_RES1]]
+; CHECK: mov {{.*}},0
define i32 @test_ctlz_64_const(i64 %x) {
entry:
@@ -393,8 +396,8 @@ entry:
}
; CHECK-LABEL: test_cttz_32
; CHECK: bsf [[REG_IF_NOTZERO:e.*]], {{.*}}
-; CHECK: mov [[REG_IF_ZERO:e.*]], 32
-; CHECK: cmovne [[REG_IF_ZERO]], [[REG_IF_NOTZERO]]
+; CHECK: mov [[REG_IF_ZERO:e.*]],32
+; CHECK: cmovne [[REG_IF_ZERO]],[[REG_IF_NOTZERO]]
define i64 @test_cttz_64(i64 %x) {
entry:
@@ -403,13 +406,13 @@ entry:
}
; CHECK-LABEL: test_cttz_64
; CHECK: bsf [[REG_IF_NOTZERO:e.*]], {{.*}}
-; CHECK: mov [[REG_RES1:e.*]], 32
-; CHECK: cmovne [[REG_RES1]], [[REG_IF_NOTZERO]]
+; CHECK: mov [[REG_RES1:e.*]],32
+; CHECK: cmovne [[REG_RES1]],[[REG_IF_NOTZERO]]
; CHECK: add [[REG_RES1]], 32
; CHECK: bsf [[REG_RES2:e.*]], [[REG_LOWER:.*]]
; CHECK: test [[REG_LOWER]], [[REG_LOWER]]
-; CHECK: cmove [[REG_RES2]], [[REG_RES1]]
-; CHECK: mov {{.*}}, 0
+; CHECK: cmove [[REG_RES2]],[[REG_RES1]]
+; CHECK: mov {{.*}},0
define i32 @test_popcount_32(i32 %x) {
entry:
@@ -417,7 +420,8 @@ entry:
ret i32 %r
}
; CHECK-LABEL: test_popcount_32
-; CHECK: call __popcountsi2
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} __popcountsi2
define i64 @test_popcount_64(i64 %x) {
entry:
@@ -425,10 +429,11 @@ entry:
ret i64 %r
}
; CHECK-LABEL: test_popcount_64
-; CHECK: call __popcountdi2
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} __popcountdi2
; __popcountdi2 only returns a 32-bit result, so clear the upper bits of
; the return value just in case.
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
define i32 @test_popcount_64_ret_i32(i64 %x) {
@@ -449,8 +454,8 @@ entry:
ret void
}
; CHECK-LABEL: test_stacksave_noalloca
-; CHECK: mov {{.*}}, esp
-; CHECK: mov esp, {{.*}}
+; CHECK: mov {{.*}},esp
+; CHECK: mov esp,{{.*}}
declare i32 @foo(i32 %x)
@@ -482,7 +487,7 @@ entry:
}
; CHECK-LABEL: test_stacksave_multiple
; At least 3 copies of esp, but probably more from having to do the allocas.
-; CHECK: mov {{.*}}, esp
-; CHECK: mov {{.*}}, esp
-; CHECK: mov {{.*}}, esp
-; CHECK: mov esp, {{.*}}
+; CHECK: mov {{.*}},esp
+; CHECK: mov {{.*}},esp
+; CHECK: mov {{.*}},esp
+; CHECK: mov esp,{{.*}}
« tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll ('K') | « tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll ('k') | tests_lit/llvm2ice_tests/nop-insertion.ll » ('j') | tests_lit/llvm2ice_tests/vector-arith.ll » ('J')

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