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Side by Side Diff: tests_lit/llvm2ice_tests/vector-select.ll

Issue 914263005: Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: fix some line wrap Created 5 years, 10 months ago
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1 ; This file tests support for the select instruction with vector valued inputs. 1 ; This file tests support for the select instruction with vector valued inputs.
2 2
3 ; RUN: %p2i -i %s --args -O2 --verbose none \ 3 ; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
4 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ 4 ; RUN: | FileCheck %s
5 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s 5 ; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
6 ; RUN: %p2i -i %s --args -Om1 --verbose none \ 6 ; RUN: | FileCheck %s
7 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ 7 ; RUN: %p2i -i %s --assemble --disassemble --args -O2 -mattr=sse4.1 \
8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s 8 ; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
9 ; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \ 9 ; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -mattr=sse4.1 \
10 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ 10 ; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
11 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
12 ; RUN: | FileCheck --check-prefix=SSE41 %s
13 ; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
14 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
15 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
16 ; RUN: | FileCheck --check-prefix=SSE41 %s
17 11
18 define <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2) { 12 define <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2) {
19 entry: 13 entry:
20 %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2 14 %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2
21 ret <16 x i8> %res 15 ret <16 x i8> %res
22 ; CHECK-LABEL: test_select_v16i8: 16 ; CHECK-LABEL: test_select_v16i8
23 ; CHECK: pand 17 ; CHECK: pand
24 ; CHECK: pandn 18 ; CHECK: pandn
25 ; CHECK: por 19 ; CHECK: por
26 20
27 ; SSE41-LABEL: test_select_v16i8: 21 ; SSE41-LABEL: test_select_v16i8
28 ; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}} 22 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
29 } 23 }
30 24
31 define <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2) { 25 define <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2) {
32 entry: 26 entry:
33 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 27 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2
34 ret <16 x i1> %res 28 ret <16 x i1> %res
35 ; CHECK-LABEL: test_select_v16i1: 29 ; CHECK-LABEL: test_select_v16i1
36 ; CHECK: pand 30 ; CHECK: pand
37 ; CHECK: pandn 31 ; CHECK: pandn
38 ; CHECK: por 32 ; CHECK: por
39 33
40 ; SSE41-LABEL: test_select_v16i1: 34 ; SSE41-LABEL: test_select_v16i1
41 ; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}} 35 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
42 } 36 }
43 37
44 define <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, <8 x i16> % arg2) { 38 define <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, <8 x i16> % arg2) {
45 entry: 39 entry:
46 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 40 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2
47 ret <8 x i16> %res 41 ret <8 x i16> %res
48 ; CHECK-LABEL: test_select_v8i16: 42 ; CHECK-LABEL: test_select_v8i16
49 ; CHECK: pand 43 ; CHECK: pand
50 ; CHECK: pandn 44 ; CHECK: pandn
51 ; CHECK: por 45 ; CHECK: por
52 46
53 ; SSE41-LABEL: test_select_v8i16: 47 ; SSE41-LABEL: test_select_v8i16
54 ; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}} 48 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
55 } 49 }
56 50
57 define <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 ) { 51 define <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 ) {
58 entry: 52 entry:
59 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 53 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2
60 ret <8 x i1> %res 54 ret <8 x i1> %res
61 ; CHECK-LABEL: test_select_v8i1: 55 ; CHECK-LABEL: test_select_v8i1
62 ; CHECK: pand 56 ; CHECK: pand
63 ; CHECK: pandn 57 ; CHECK: pandn
64 ; CHECK: por 58 ; CHECK: por
65 59
66 ; SSE41-LABEL: test_select_v8i1: 60 ; SSE41-LABEL: test_select_v8i1
67 ; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}} 61 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
68 } 62 }
69 63
70 define <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, <4 x i32> % arg2) { 64 define <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, <4 x i32> % arg2) {
71 entry: 65 entry:
72 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 66 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2
73 ret <4 x i32> %res 67 ret <4 x i32> %res
74 ; CHECK-LABEL: test_select_v4i32: 68 ; CHECK-LABEL: test_select_v4i32
75 ; CHECK: pand 69 ; CHECK: pand
76 ; CHECK: pandn 70 ; CHECK: pandn
77 ; CHECK: por 71 ; CHECK: por
78 72
79 ; SSE41-LABEL: test_select_v4i32: 73 ; SSE41-LABEL: test_select_v4i32
80 ; SSE41: pslld xmm0, 31 74 ; SSE41: pslld xmm0,0x1f
81 ; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}} 75 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
82 } 76 }
83 77
84 define <4 x float> @test_select_v4f32(<4 x i1> %cond, <4 x float> %arg1, <4 x fl oat> %arg2) { 78 define <4 x float> @test_select_v4f32(<4 x i1> %cond, <4 x float> %arg1, <4 x fl oat> %arg2) {
85 entry: 79 entry:
86 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 80 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2
87 ret <4 x float> %res 81 ret <4 x float> %res
88 ; CHECK-LABEL: test_select_v4f32: 82 ; CHECK-LABEL: test_select_v4f32
89 ; CHECK: pand 83 ; CHECK: pand
90 ; CHECK: pandn 84 ; CHECK: pandn
91 ; CHECK: por 85 ; CHECK: por
92 86
93 ; SSE41-LABEL: test_select_v4f32: 87 ; SSE41-LABEL: test_select_v4f32
94 ; SSE41: pslld xmm0, 31 88 ; SSE41: pslld xmm0,0x1f
95 ; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}} 89 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
96 } 90 }
97 91
98 define <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 ) { 92 define <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 ) {
99 entry: 93 entry:
100 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 94 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2
101 ret <4 x i1> %res 95 ret <4 x i1> %res
102 ; CHECK-LABEL: test_select_v4i1: 96 ; CHECK-LABEL: test_select_v4i1
103 ; CHECK: pand 97 ; CHECK: pand
104 ; CHECK: pandn 98 ; CHECK: pandn
105 ; CHECK: por 99 ; CHECK: por
106 100
107 ; SSE41-LABEL: test_select_v4i1: 101 ; SSE41-LABEL: test_select_v4i1
108 ; SSE41: pslld xmm0, 31 102 ; SSE41: pslld xmm0,0x1f
109 ; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}} 103 ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
110 } 104 }
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