Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(1010)

Side by Side Diff: tests_lit/llvm2ice_tests/select-opt.ll

Issue 914263005: Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: fix some line wrap Created 5 years, 10 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « tests_lit/llvm2ice_tests/sdiv.ll ('k') | tests_lit/llvm2ice_tests/shift.ll » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 ; Simple test of the select instruction. The CHECK lines are only 1 ; Simple test of the select instruction. The CHECK lines are only
2 ; checking for basic instruction patterns that should be present 2 ; checking for basic instruction patterns that should be present
3 ; regardless of the optimization level, so there are no special OPTM1 3 ; regardless of the optimization level, so there are no special OPTM1
4 ; match lines. 4 ; match lines.
5 5
6 ; RUN: %p2i -i %s --args -O2 --verbose none \ 6 ; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
7 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ 7 ; RUN: | FileCheck %s
8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s 8 ; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
9 ; RUN: %p2i -i %s --args -Om1 --verbose none \ 9 ; RUN: | FileCheck %s
10 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
11 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
12 10
13 define void @testSelect(i32 %a, i32 %b) { 11 define void @testSelect(i32 %a, i32 %b) {
14 entry: 12 entry:
15 %cmp = icmp slt i32 %a, %b 13 %cmp = icmp slt i32 %a, %b
16 %cond = select i1 %cmp, i32 %a, i32 %b 14 %cond = select i1 %cmp, i32 %a, i32 %b
17 tail call void @useInt(i32 %cond) 15 tail call void @useInt(i32 %cond)
18 %cmp1 = icmp sgt i32 %a, %b 16 %cmp1 = icmp sgt i32 %a, %b
19 %cond2 = select i1 %cmp1, i32 10, i32 20 17 %cond2 = select i1 %cmp1, i32 10, i32 20
20 tail call void @useInt(i32 %cond2) 18 tail call void @useInt(i32 %cond2)
21 ret void 19 ret void
22 } 20 }
23 21
24 define void @useInt(i32 %x) { 22 declare void @useInt(i32 %x)
25 entry:
26 call void @useIntHelper(i32 %x)
27 ret void
28 }
29
30 declare void @useIntHelper(i32)
31 23
32 ; CHECK-LABEL: testSelect 24 ; CHECK-LABEL: testSelect
33 ; CHECK: cmp 25 ; CHECK: cmp
34 ; CHECK: cmp 26 ; CHECK: cmp
35 ; CHECK: call useInt 27 ; CHECK: call {{.*}} R_{{.*}} useInt
36 ; CHECK: cmp 28 ; CHECK: cmp
37 ; CHECK: cmp 29 ; CHECK: cmp
38 ; CHECK: call useInt 30 ; CHECK: call {{.*}} R_{{.*}} useInt
39 ; CHECK: ret 31 ; CHECK: ret
40 32
41 ; Check for valid addressing mode in the cmp instruction when the 33 ; Check for valid addressing mode in the cmp instruction when the
42 ; operand is an immediate. 34 ; operand is an immediate.
43 define i32 @testSelectImm32(i32 %a, i32 %b) { 35 define i32 @testSelectImm32(i32 %a, i32 %b) {
44 entry: 36 entry:
45 %cond = select i1 false, i32 %a, i32 %b 37 %cond = select i1 false, i32 %a, i32 %b
46 ret i32 %cond 38 ret i32 %cond
47 } 39 }
48 ; CHECK-LABEL: testSelectImm32 40 ; CHECK-LABEL: testSelectImm32
49 ; CHECK-NOT: cmp {{[0-9]+}}, 41 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
50 42
51 ; Check for valid addressing mode in the cmp instruction when the 43 ; Check for valid addressing mode in the cmp instruction when the
52 ; operand is an immediate. There is a different x86-32 lowering 44 ; operand is an immediate. There is a different x86-32 lowering
53 ; sequence for 64-bit operands. 45 ; sequence for 64-bit operands.
54 define i64 @testSelectImm64(i64 %a, i64 %b) { 46 define i64 @testSelectImm64(i64 %a, i64 %b) {
55 entry: 47 entry:
56 %cond = select i1 true, i64 %a, i64 %b 48 %cond = select i1 true, i64 %a, i64 %b
57 ret i64 %cond 49 ret i64 %cond
58 } 50 }
59 ; CHECK-LABEL: testSelectImm64 51 ; CHECK-LABEL: testSelectImm64
60 ; CHECK-NOT: cmp {{[0-9]+}}, 52 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
OLDNEW
« no previous file with comments | « tests_lit/llvm2ice_tests/sdiv.ll ('k') | tests_lit/llvm2ice_tests/shift.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698