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Side by Side Diff: tests_lit/llvm2ice_tests/vector-cast.ll

Issue 914263005: Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 10 months ago
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1 ; This file tests casting / conversion operations that apply to vector types. 1 ; This file tests casting / conversion operations that apply to vector types.
2 ; bitcast operations are in vector-bitcast.ll. 2 ; bitcast operations are in vector-bitcast.ll.
3 3
4 ; RUN: %p2i -i %s --args -O2 --verbose none \ 4 ; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
5 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ 5 ; RUN: | FileCheck %s
6 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s 6 ; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
7 ; RUN: %p2i -i %s --args -Om1 --verbose none \ 7 ; RUN: | FileCheck %s
8 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
9 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
10 8
11 ; sext operations 9 ; sext operations
12 10
13 define <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) { 11 define <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) {
14 entry: 12 entry:
15 %res = sext <16 x i1> %arg to <16 x i8> 13 %res = sext <16 x i1> %arg to <16 x i8>
16 ret <16 x i8> %res 14 ret <16 x i8> %res
17 15
18 ; CHECK-LABEL: test_sext_v16i1_to_v16i8: 16 ; CHECK-LABEL: test_sext_v16i1_to_v16i8
19 ; CHECK: pxor 17 ; CHECK: pxor
20 ; CHECK: pcmpeqb 18 ; CHECK: pcmpeqb
21 ; CHECK: psubb 19 ; CHECK: psubb
22 ; CHECK: pand 20 ; CHECK: pand
23 ; CHECK: pxor 21 ; CHECK: pxor
24 ; CHECK: pcmpgtb 22 ; CHECK: pcmpgtb
25 } 23 }
26 24
27 define <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) { 25 define <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) {
28 entry: 26 entry:
29 %res = sext <8 x i1> %arg to <8 x i16> 27 %res = sext <8 x i1> %arg to <8 x i16>
30 ret <8 x i16> %res 28 ret <8 x i16> %res
31 29
32 ; CHECK-LABEL: test_sext_v8i1_to_v8i16: 30 ; CHECK-LABEL: test_sext_v8i1_to_v8i16
33 ; CHECK: psllw {{.*}}, 15 31 ; CHECK: psllw {{.*}}, 15
34 ; CHECK: psraw {{.*}}, 15 32 ; CHECK: psraw {{.*}}, 15
35 } 33 }
36 34
37 define <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) { 35 define <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) {
38 entry: 36 entry:
39 %res = sext <4 x i1> %arg to <4 x i32> 37 %res = sext <4 x i1> %arg to <4 x i32>
40 ret <4 x i32> %res 38 ret <4 x i32> %res
41 39
42 ; CHECK-LABEL: test_sext_v4i1_to_v4i32: 40 ; CHECK-LABEL: test_sext_v4i1_to_v4i32
43 ; CHECK: pslld {{.*}}, 31 41 ; CHECK: pslld {{.*}}, 31
44 ; CHECK: psrad {{.*}}, 31 42 ; CHECK: psrad {{.*}}, 31
45 } 43 }
46 44
47 ; zext operations 45 ; zext operations
48 46
49 define <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) { 47 define <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) {
50 entry: 48 entry:
51 %res = zext <16 x i1> %arg to <16 x i8> 49 %res = zext <16 x i1> %arg to <16 x i8>
52 ret <16 x i8> %res 50 ret <16 x i8> %res
53 51
54 ; CHECK-LABEL: test_zext_v16i1_to_v16i8: 52 ; CHECK-LABEL: test_zext_v16i1_to_v16i8
55 ; CHECK: pxor 53 ; CHECK: pxor
56 ; CHECK: pcmpeqb 54 ; CHECK: pcmpeqb
57 ; CHECK: psubb 55 ; CHECK: psubb
58 ; CHECK: pand 56 ; CHECK: pand
59 } 57 }
60 58
61 define <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) { 59 define <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) {
62 entry: 60 entry:
63 %res = zext <8 x i1> %arg to <8 x i16> 61 %res = zext <8 x i1> %arg to <8 x i16>
64 ret <8 x i16> %res 62 ret <8 x i16> %res
65 63
66 ; CHECK-LABEL: test_zext_v8i1_to_v8i16: 64 ; CHECK-LABEL: test_zext_v8i1_to_v8i16
67 ; CHECK: pxor 65 ; CHECK: pxor
68 ; CHECK: pcmpeqw 66 ; CHECK: pcmpeqw
69 ; CHECK: psubw 67 ; CHECK: psubw
70 ; CHECK: pand 68 ; CHECK: pand
71 } 69 }
72 70
73 define <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) { 71 define <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) {
74 entry: 72 entry:
75 %res = zext <4 x i1> %arg to <4 x i32> 73 %res = zext <4 x i1> %arg to <4 x i32>
76 ret <4 x i32> %res 74 ret <4 x i32> %res
77 75
78 ; CHECK-LABEL: test_zext_v4i1_to_v4i32: 76 ; CHECK-LABEL: test_zext_v4i1_to_v4i32
79 ; CHECK: pxor 77 ; CHECK: pxor
80 ; CHECK: pcmpeqd 78 ; CHECK: pcmpeqd
81 ; CHECK: psubd 79 ; CHECK: psubd
82 ; CHECK: pand 80 ; CHECK: pand
83 } 81 }
84 82
85 ; trunc operations 83 ; trunc operations
86 84
87 define <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) { 85 define <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) {
88 entry: 86 entry:
89 %res = trunc <16 x i8> %arg to <16 x i1> 87 %res = trunc <16 x i8> %arg to <16 x i1>
90 ret <16 x i1> %res 88 ret <16 x i1> %res
91 89
92 ; CHECK-LABEL: test_trunc_v16i8_to_v16i1: 90 ; CHECK-LABEL: test_trunc_v16i8_to_v16i1
93 ; CHECK: pxor 91 ; CHECK: pxor
94 ; CHECK: pcmpeqb 92 ; CHECK: pcmpeqb
95 ; CHECK: psubb 93 ; CHECK: psubb
96 ; CHECK: pand 94 ; CHECK: pand
97 } 95 }
98 96
99 define <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) { 97 define <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) {
100 entry: 98 entry:
101 %res = trunc <8 x i16> %arg to <8 x i1> 99 %res = trunc <8 x i16> %arg to <8 x i1>
102 ret <8 x i1> %res 100 ret <8 x i1> %res
103 101
104 ; CHECK-LABEL: test_trunc_v8i16_to_v8i1: 102 ; CHECK-LABEL: test_trunc_v8i16_to_v8i1
105 ; CHECK: pxor 103 ; CHECK: pxor
106 ; CHECK: pcmpeqw 104 ; CHECK: pcmpeqw
107 ; CHECK: psubw 105 ; CHECK: psubw
108 ; CHECK: pand 106 ; CHECK: pand
109 } 107 }
110 108
111 define <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) { 109 define <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) {
112 entry: 110 entry:
113 %res = trunc <4 x i32> %arg to <4 x i1> 111 %res = trunc <4 x i32> %arg to <4 x i1>
114 ret <4 x i1> %res 112 ret <4 x i1> %res
115 113
116 ; CHECK-LABEL: test_trunc_v4i32_to_v4i1: 114 ; CHECK-LABEL: test_trunc_v4i32_to_v4i1
117 ; CHECK: pxor 115 ; CHECK: pxor
118 ; CHECK: pcmpeqd 116 ; CHECK: pcmpeqd
119 ; CHECK: psubd 117 ; CHECK: psubd
120 ; CHECK: pand 118 ; CHECK: pand
121 } 119 }
122 120
123 ; fpto[us]i operations 121 ; fpto[us]i operations
124 122
125 define <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) { 123 define <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) {
126 entry: 124 entry:
127 %res = fptosi <4 x float> %arg to <4 x i32> 125 %res = fptosi <4 x float> %arg to <4 x i32>
128 ret <4 x i32> %res 126 ret <4 x i32> %res
129 127
130 ; CHECK-LABEL: test_fptosi_v4f32_to_v4i32: 128 ; CHECK-LABEL: test_fptosi_v4f32_to_v4i32
131 ; CHECK: cvttps2dq 129 ; CHECK: cvttps2dq
132 } 130 }
133 131
134 define <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) { 132 define <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) {
135 entry: 133 entry:
136 %res = fptoui <4 x float> %arg to <4 x i32> 134 %res = fptoui <4 x float> %arg to <4 x i32>
137 ret <4 x i32> %res 135 ret <4 x i32> %res
138 136
139 ; CHECK-LABEL: test_fptoui_v4f32_to_v4i32: 137 ; CHECK-LABEL: test_fptoui_v4f32_to_v4i32
140 ; CHECK: call Sz_fptoui_v4f32 138 ; CHECK: call
139 ; CHECK-NEXT: R_{{.*}} Sz_fptoui_v4f32
141 } 140 }
142 141
143 ; [su]itofp operations 142 ; [su]itofp operations
144 143
145 define <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) { 144 define <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) {
146 entry: 145 entry:
147 %res = sitofp <4 x i32> %arg to <4 x float> 146 %res = sitofp <4 x i32> %arg to <4 x float>
148 ret <4 x float> %res 147 ret <4 x float> %res
149 148
150 ; CHECK-LABEL: test_sitofp_v4i32_to_v4f32: 149 ; CHECK-LABEL: test_sitofp_v4i32_to_v4f32
151 ; CHECK: cvtdq2ps 150 ; CHECK: cvtdq2ps
152 } 151 }
153 152
154 define <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { 153 define <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) {
155 entry: 154 entry:
156 %res = uitofp <4 x i32> %arg to <4 x float> 155 %res = uitofp <4 x i32> %arg to <4 x float>
157 ret <4 x float> %res 156 ret <4 x float> %res
158 157
159 ; CHECK-LABEL: test_uitofp_v4i32_to_v4f32: 158 ; CHECK-LABEL: test_uitofp_v4i32_to_v4f32
160 ; CHECK: call Sz_uitofp_v4i32 159 ; CHECK: call
160 ; CHECK-NEXT: R_{{.*}} Sz_uitofp_v4i32
161 } 161 }
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