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1 ; Simple test of the select instruction. The CHECK lines are only | 1 ; Simple test of the select instruction. The CHECK lines are only |
2 ; checking for basic instruction patterns that should be present | 2 ; checking for basic instruction patterns that should be present |
3 ; regardless of the optimization level, so there are no special OPTM1 | 3 ; regardless of the optimization level, so there are no special OPTM1 |
4 ; match lines. | 4 ; match lines. |
5 | 5 |
6 ; RUN: %p2i -i %s --args -O2 --verbose none \ | 6 ; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \ |
7 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ | 7 ; RUN: | FileCheck %s |
8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | 8 ; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \ |
9 ; RUN: %p2i -i %s --args -Om1 --verbose none \ | 9 ; RUN: | FileCheck %s |
10 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ | |
11 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | |
12 | 10 |
13 define void @testSelect(i32 %a, i32 %b) { | 11 define void @testSelect(i32 %a, i32 %b) { |
14 entry: | 12 entry: |
15 %cmp = icmp slt i32 %a, %b | 13 %cmp = icmp slt i32 %a, %b |
16 %cond = select i1 %cmp, i32 %a, i32 %b | 14 %cond = select i1 %cmp, i32 %a, i32 %b |
17 tail call void @useInt(i32 %cond) | 15 tail call void @useInt(i32 %cond) |
18 %cmp1 = icmp sgt i32 %a, %b | 16 %cmp1 = icmp sgt i32 %a, %b |
19 %cond2 = select i1 %cmp1, i32 10, i32 20 | 17 %cond2 = select i1 %cmp1, i32 10, i32 20 |
20 tail call void @useInt(i32 %cond2) | 18 tail call void @useInt(i32 %cond2) |
21 ret void | 19 ret void |
22 } | 20 } |
23 | 21 |
24 define void @useInt(i32 %x) { | 22 define void @useInt(i32 %x) { |
25 entry: | 23 entry: |
26 call void @useIntHelper(i32 %x) | 24 call void @useIntHelper(i32 %x) |
27 ret void | 25 ret void |
28 } | 26 } |
29 | 27 |
30 declare void @useIntHelper(i32) | 28 declare void @useIntHelper(i32) |
31 | 29 |
32 ; CHECK-LABEL: testSelect | 30 ; CHECK-LABEL: testSelect |
33 ; CHECK: cmp | 31 ; CHECK: cmp |
34 ; CHECK: cmp | 32 ; CHECK: cmp |
35 ; CHECK: call useInt | 33 ; CHECK: call |
| 34 ; CHECK-NEXT: R_{{.*}} useInt |
36 ; CHECK: cmp | 35 ; CHECK: cmp |
37 ; CHECK: cmp | 36 ; CHECK: cmp |
38 ; CHECK: call useInt | 37 ; CHECK: call |
| 38 ; CHECK-NEXT: R_{{.*}} useInt |
39 ; CHECK: ret | 39 ; CHECK: ret |
40 | 40 |
41 ; Check for valid addressing mode in the cmp instruction when the | 41 ; Check for valid addressing mode in the cmp instruction when the |
42 ; operand is an immediate. | 42 ; operand is an immediate. |
43 define i32 @testSelectImm32(i32 %a, i32 %b) { | 43 define i32 @testSelectImm32(i32 %a, i32 %b) { |
44 entry: | 44 entry: |
45 %cond = select i1 false, i32 %a, i32 %b | 45 %cond = select i1 false, i32 %a, i32 %b |
46 ret i32 %cond | 46 ret i32 %cond |
47 } | 47 } |
48 ; CHECK-LABEL: testSelectImm32 | 48 ; CHECK-LABEL: testSelectImm32 |
49 ; CHECK-NOT: cmp {{[0-9]+}}, | 49 ; CHECK-NOT: cmp {{[0-9]+}}, |
50 | 50 |
51 ; Check for valid addressing mode in the cmp instruction when the | 51 ; Check for valid addressing mode in the cmp instruction when the |
52 ; operand is an immediate. There is a different x86-32 lowering | 52 ; operand is an immediate. There is a different x86-32 lowering |
53 ; sequence for 64-bit operands. | 53 ; sequence for 64-bit operands. |
54 define i64 @testSelectImm64(i64 %a, i64 %b) { | 54 define i64 @testSelectImm64(i64 %a, i64 %b) { |
55 entry: | 55 entry: |
56 %cond = select i1 true, i64 %a, i64 %b | 56 %cond = select i1 true, i64 %a, i64 %b |
57 ret i64 %cond | 57 ret i64 %cond |
58 } | 58 } |
59 ; CHECK-LABEL: testSelectImm64 | 59 ; CHECK-LABEL: testSelectImm64 |
60 ; CHECK-NOT: cmp {{[0-9]+}}, | 60 ; CHECK-NOT: cmp {{[0-9]+}}, |
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