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1 ; This is a regression test that idiv and div operands are legalized | 1 ; This is a regression test that idiv and div operands are legalized |
2 ; (they cannot be constants and can only be reg/mem for x86). | 2 ; (they cannot be constants and can only be reg/mem for x86). |
3 | 3 |
4 ; RUN: %p2i -i %s --args -O2 --verbose none \ | 4 ; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \ |
5 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ | 5 ; RUN: | FileCheck %s |
6 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | 6 ; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \ |
7 ; RUN: %p2i -i %s --args -Om1 --verbose none \ | 7 ; RUN: | FileCheck %s |
8 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ | |
9 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | |
10 | 8 |
11 define i32 @Sdiv_const8_b(i8 %a) { | 9 define i32 @Sdiv_const8_b(i8 %a) { |
12 ; CHECK-LABEL: Sdiv_const8_b | 10 ; CHECK-LABEL: Sdiv_const8_b |
13 entry: | 11 entry: |
14 %div = sdiv i8 %a, 12 | 12 %div = sdiv i8 %a, 12 |
15 ; CHECK: mov {{.*}}, 12 | 13 ; CHECK: mov {{.*}},12 |
16 ; CHECK-NOT: idiv 12 | 14 ; CHECK-NOT: idiv 12 |
17 %div_ext = sext i8 %div to i32 | 15 %div_ext = sext i8 %div to i32 |
18 ret i32 %div_ext | 16 ret i32 %div_ext |
19 } | 17 } |
20 | 18 |
21 define i32 @Sdiv_const16_b(i16 %a) { | 19 define i32 @Sdiv_const16_b(i16 %a) { |
22 ; CHECK-LABEL: Sdiv_const16_b | 20 ; CHECK-LABEL: Sdiv_const16_b |
23 entry: | 21 entry: |
24 %div = sdiv i16 %a, 1234 | 22 %div = sdiv i16 %a, 1234 |
25 ; CHECK: mov {{.*}}, 1234 | 23 ; CHECK: mov {{.*}},1234 |
26 ; CHECK-NOT: idiv 1234 | 24 ; CHECK-NOT: idiv 1234 |
27 %div_ext = sext i16 %div to i32 | 25 %div_ext = sext i16 %div to i32 |
28 ret i32 %div_ext | 26 ret i32 %div_ext |
29 } | 27 } |
30 | 28 |
31 define i32 @Sdiv_const32_b(i32 %a) { | 29 define i32 @Sdiv_const32_b(i32 %a) { |
32 ; CHECK-LABEL: Sdiv_const32_b | 30 ; CHECK-LABEL: Sdiv_const32_b |
33 entry: | 31 entry: |
34 %div = sdiv i32 %a, 1234 | 32 %div = sdiv i32 %a, 1234 |
35 ; CHECK: mov {{.*}}, 1234 | 33 ; CHECK: mov {{.*}},1234 |
36 ; CHECK-NOT: idiv 1234 | 34 ; CHECK-NOT: idiv 1234 |
37 ret i32 %div | 35 ret i32 %div |
38 } | 36 } |
39 | 37 |
40 define i32 @Srem_const_b(i32 %a) { | 38 define i32 @Srem_const_b(i32 %a) { |
41 ; CHECK-LABEL: Srem_const_b | 39 ; CHECK-LABEL: Srem_const_b |
42 entry: | 40 entry: |
43 %rem = srem i32 %a, 2345 | 41 %rem = srem i32 %a, 2345 |
44 ; CHECK: mov {{.*}}, 2345 | 42 ; CHECK: mov {{.*}},2345 |
45 ; CHECK-NOT: idiv 2345 | 43 ; CHECK-NOT: idiv 2345 |
46 ret i32 %rem | 44 ret i32 %rem |
47 } | 45 } |
48 | 46 |
49 define i32 @Udiv_const_b(i32 %a) { | 47 define i32 @Udiv_const_b(i32 %a) { |
50 ; CHECK-LABEL: Udiv_const_b | 48 ; CHECK-LABEL: Udiv_const_b |
51 entry: | 49 entry: |
52 %div = udiv i32 %a, 3456 | 50 %div = udiv i32 %a, 3456 |
53 ; CHECK: mov {{.*}}, 3456 | 51 ; CHECK: mov {{.*}},3456 |
54 ; CHECK-NOT: div 3456 | 52 ; CHECK-NOT: div 3456 |
55 ret i32 %div | 53 ret i32 %div |
56 } | 54 } |
57 | 55 |
58 define i32 @Urem_const_b(i32 %a) { | 56 define i32 @Urem_const_b(i32 %a) { |
59 ; CHECK-LABEL: Urem_const_b | 57 ; CHECK-LABEL: Urem_const_b |
60 entry: | 58 entry: |
61 %rem = urem i32 %a, 4567 | 59 %rem = urem i32 %a, 4567 |
62 ; CHECK: mov {{.*}}, 4567 | 60 ; CHECK: mov {{.*}},4567 |
63 ; CHECK-NOT: div 4567 | 61 ; CHECK-NOT: div 4567 |
64 ret i32 %rem | 62 ret i32 %rem |
65 } | 63 } |
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