Port flow_graph*, disassembler to ISL_Print

runtime/vm/flow_graph_allocator.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/flow_graph_allocator.h"
 
 #include "vm/bit_vector.h"
 #include "vm/intermediate_language.h"
 #include "vm/il_printer.h"
 #include "vm/flow_graph.h"
 #include "vm/flow_graph_compiler.h"
+#include "vm/log.h"
 #include "vm/parser.h"
 
 namespace dart {
 
 DEFINE_FLAG(bool, print_ssa_liveness, false,
             "Print liveness for ssa variables.");
 DEFINE_FLAG(bool, trace_ssa_allocator, false,
             "Trace register allocation over SSA.");
 DEFINE_FLAG(bool, print_ssa_liveranges, false,
             "Print live ranges after allocation.");
@@ skipping 419 matching lines @@
     UNREACHABLE();
   }
 }
 
 
 void LiveRange::Print() {
   if (first_use_interval() == NULL) {
     return;
   }
 
-  OS::Print("  live range v%" Pd " [%" Pd ", %" Pd ") in ", vreg(),
+  ISL_Print("  live range v%" Pd " [%" Pd ", %" Pd ") in ", vreg(),
                                                             Start(),
                                                             End());
   assigned_location().Print();
   if (spill_slot_.HasStackIndex()) {
     intptr_t stack_slot = spill_slot_.stack_index();
-    OS::Print(" allocated spill slot: %" Pd "", stack_slot);
+    ISL_Print(" allocated spill slot: %" Pd "", stack_slot);
   }
-  OS::Print("\n");
+  ISL_Print("\n");
 
   SafepointPosition* safepoint = first_safepoint();
   while (safepoint != NULL) {
-    OS::Print("    Safepoint [%" Pd "]: ", safepoint->pos());
+    ISL_Print("    Safepoint [%" Pd "]: ", safepoint->pos());
     safepoint->locs()->stack_bitmap()->Print();
-    OS::Print("\n");
+    ISL_Print("\n");
     safepoint = safepoint->next();
   }
 
   UsePosition* use_pos = uses_;
   for (UseInterval* interval = first_use_interval_;
        interval != NULL;
        interval = interval->next()) {
-    OS::Print("    use interval [%" Pd ", %" Pd ")\n",
+    ISL_Print("    use interval [%" Pd ", %" Pd ")\n",
               interval->start(),
               interval->end());
     while ((use_pos != NULL) && (use_pos->pos() <= interval->end())) {
-      OS::Print("      use at %" Pd "", use_pos->pos());
+      ISL_Print("      use at %" Pd "", use_pos->pos());
       if (use_pos->location_slot() != NULL) {
-        OS::Print(" as ");
+        ISL_Print(" as ");
         use_pos->location_slot()->Print();
       }
-      OS::Print("\n");
+      ISL_Print("\n");
       use_pos = use_pos->next();
     }
   }
 
   if (next_sibling() != NULL) {
     next_sibling()->Print();
   }
 }
 
 
@@ skipping 1282 matching lines @@
   UseInterval* last_use_interval = (last_before_split == last_use_interval_) ?
     first_after_split : last_use_interval_;
   next_sibling_ = new LiveRange(vreg(),
                                 representation(),
                                 first_use_after_split,
                                 first_after_split,
                                 last_use_interval,
                                 first_safepoint_after_split,
                                 next_sibling_);
 
-  TRACE_ALLOC(OS::Print("  split sibling [%" Pd ", %" Pd ")\n",
+  TRACE_ALLOC(ISL_Print("  split sibling [%" Pd ", %" Pd ")\n",
                         next_sibling_->Start(), next_sibling_->End()));
 
   last_use_interval_ = last_before_split;
   last_use_interval_->next_ = NULL;
 
   if (first_use_after_split != NULL) {
     finger_.UpdateAfterSplit(first_use_after_split->pos());
   }
 
   return next_sibling_;
 }
 
 
 LiveRange* FlowGraphAllocator::SplitBetween(LiveRange* range,
                                             intptr_t from,
                                             intptr_t to) {
-  TRACE_ALLOC(OS::Print("split v%" Pd " [%" Pd ", %" Pd
+  TRACE_ALLOC(ISL_Print("split v%" Pd " [%" Pd ", %" Pd
                         ") between [%" Pd ", %" Pd ")\n",
                         range->vreg(), range->Start(), range->End(), from, to));
 
   intptr_t split_pos = kIllegalPosition;
 
   BlockInfo* split_block = BlockInfoAt(to);
   if (from < split_block->entry()->lifetime_position()) {
     // Interval [from, to) spans multiple blocks.
 
     // If last block is inside a loop prefer splitting at outermost loop's
@@ skipping 19 matching lines @@
   ASSERT(from < split_pos);
 
   return range->SplitAt(split_pos);
 }
 
 
 void FlowGraphAllocator::SpillBetween(LiveRange* range,
                                       intptr_t from,
                                       intptr_t to) {
   ASSERT(from < to);
-  TRACE_ALLOC(OS::Print("spill v%" Pd " [%" Pd ", %" Pd ") "
+  TRACE_ALLOC(ISL_Print("spill v%" Pd " [%" Pd ", %" Pd ") "
                         "between [%" Pd ", %" Pd ")\n",
                         range->vreg(), range->Start(), range->End(), from, to));
   LiveRange* tail = range->SplitAt(from);
 
   if (tail->Start() < to) {
     // There is an intersection of tail and [from, to).
     LiveRange* tail_tail = SplitBetween(tail, tail->Start(), to);
     Spill(tail);
     AddToUnallocated(tail_tail);
   } else {
     // No intersection between tail and [from, to).
     AddToUnallocated(tail);
   }
 }
 
 
 void FlowGraphAllocator::SpillAfter(LiveRange* range, intptr_t from) {
-  TRACE_ALLOC(OS::Print("spill v%" Pd " [%" Pd ", %" Pd ") after %" Pd "\n",
+  TRACE_ALLOC(ISL_Print("spill v%" Pd " [%" Pd ", %" Pd ") after %" Pd "\n",
                         range->vreg(), range->Start(), range->End(), from));
 
   // When spilling the value inside the loop check if this spill can
   // be moved outside.
   BlockInfo* block_info = BlockInfoAt(from);
   if (block_info->is_loop_header() || (block_info->loop() != NULL)) {
     BlockInfo* loop_header =
         block_info->is_loop_header() ? block_info : block_info->loop();
 
     if ((range->Start() <= loop_header->entry()->start_pos()) &&
         RangeHasOnlyUnconstrainedUsesInLoop(range, loop_header->loop_id())) {
       ASSERT(loop_header->entry()->start_pos() <= from);
       from = loop_header->entry()->start_pos();
-      TRACE_ALLOC(OS::Print("  moved spill position to loop header %" Pd "\n",
+      TRACE_ALLOC(ISL_Print("  moved spill position to loop header %" Pd "\n",
                             from));
     }
   }
 
   LiveRange* tail = range->SplitAt(from);
   Spill(tail);
 }
 
 
 void FlowGraphAllocator::AllocateSpillSlotFor(LiveRange* range) {
@@ skipping 211 matching lines @@
   // If hint is available try hint first.
   // TODO(vegorov): ensure that phis are hinted on the back edge.
   Location hint = unallocated->finger()->FirstHint();
   if (hint.IsMachineRegister()) {
     if (!blocked_registers_[hint.register_code()]) {
       free_until = FirstIntersectionWithAllocated(hint.register_code(),
                                                   unallocated);
       candidate = hint.register_code();
     }
 
-    TRACE_ALLOC(OS::Print("found hint %s for v%" Pd ": free until %" Pd "\n",
+    TRACE_ALLOC(ISL_Print("found hint %s for v%" Pd ": free until %" Pd "\n",
                           hint.Name(),
                           unallocated->vreg(),
                           free_until));
   } else {
     for (intptr_t reg = 0; reg < NumberOfRegisters(); ++reg) {
       if (!blocked_registers_[reg] && (registers_[reg]->length() == 0)) {
         candidate = reg;
         free_until = kMaxPosition;
         break;
       }
@@ skipping 42 matching lines @@
       if (range->assigned_location().kind() == register_kind_) {
         const intptr_t reg = range->assigned_location().register_code();
 
         if (!reaching_defs_.Get(phi)->Contains(unallocated->vreg())) {
           used_on_backedge[reg] = true;
         }
       }
     }
 
     if (used_on_backedge[candidate]) {
-      TRACE_ALLOC(OS::Print(
+      TRACE_ALLOC(ISL_Print(
           "considering %s for v%" Pd ": has interference on the back edge"
           " {loop [%" Pd ", %" Pd ")}\n",
           MakeRegisterLocation(candidate).Name(),
           unallocated->vreg(),
           loop_header->entry()->start_pos(),
           loop_header->last_block()->end_pos()));
       for (intptr_t reg = 0; reg < NumberOfRegisters(); ++reg) {
         if (blocked_registers_[reg] ||
             (reg == candidate) ||
             used_on_backedge[reg]) {
           continue;
         }
 
         const intptr_t intersection =
             FirstIntersectionWithAllocated(reg, unallocated);
         if (intersection >= free_until) {
           candidate = reg;
           free_until = intersection;
-          TRACE_ALLOC(OS::Print(
+          TRACE_ALLOC(ISL_Print(
               "found %s for v%" Pd " with no interference on the back edge\n",
               MakeRegisterLocation(candidate).Name(),
               candidate));
           break;
         }
       }
     }
   }
 
-  TRACE_ALLOC(OS::Print("assigning free register "));
+  TRACE_ALLOC(ISL_Print("assigning free register "));
   TRACE_ALLOC(MakeRegisterLocation(candidate).Print());
-  TRACE_ALLOC(OS::Print(" to v%" Pd "\n", unallocated->vreg()));
+  TRACE_ALLOC(ISL_Print(" to v%" Pd "\n", unallocated->vreg()));
 
   if (free_until != kMaxPosition) {
     // There was an intersection. Split unallocated.
-    TRACE_ALLOC(OS::Print("  splitting at %" Pd "\n", free_until));
+    TRACE_ALLOC(ISL_Print("  splitting at %" Pd "\n", free_until));
     LiveRange* tail = unallocated->SplitAt(free_until);
     AddToUnallocated(tail);
   }
 
   registers_[candidate]->Add(unallocated);
   unallocated->set_assigned_location(MakeRegisterLocation(candidate));
 
   return true;
 }
 
@@ skipping 78 matching lines @@
                              : unallocated->Start();
   if (free_until < register_use_pos) {
     // Can't acquire free register. Spill until we really need one.
     ASSERT(unallocated->Start() < ToInstructionStart(register_use_pos));
     SpillBetween(unallocated, unallocated->Start(), register_use->pos());
     return;
   }
 
   ASSERT(candidate != kNoRegister);
 
-  TRACE_ALLOC(OS::Print("assigning blocked register "));
+  TRACE_ALLOC(ISL_Print("assigning blocked register "));
   TRACE_ALLOC(MakeRegisterLocation(candidate).Print());
-  TRACE_ALLOC(OS::Print(" to live range v%" Pd " until %" Pd "\n",
+  TRACE_ALLOC(ISL_Print(" to live range v%" Pd " until %" Pd "\n",
                         unallocated->vreg(), blocked_at));
 
   if (blocked_at < unallocated->End()) {
     // Register is blocked before the end of the live range.  Split the range
     // at latest at blocked_at position.
     LiveRange* tail = SplitBetween(unallocated,
                                    unallocated->Start(),
                                    blocked_at + 1);
     AddToUnallocated(tail);
   }
@@ skipping 144 matching lines @@
 
   return parallel_move->AddMove(to, from);
 }
 
 
 void FlowGraphAllocator::ConvertUseTo(UsePosition* use, Location loc) {
   ASSERT(!loc.IsPairLocation());
   ASSERT(use->location_slot() != NULL);
   Location* slot = use->location_slot();
   ASSERT(slot->IsUnallocated());
-  TRACE_ALLOC(OS::Print("  use at %" Pd " converted to ", use->pos()));
+  TRACE_ALLOC(ISL_Print("  use at %" Pd " converted to ", use->pos()));
   TRACE_ALLOC(loc.Print());
-  TRACE_ALLOC(OS::Print("\n"));
+  TRACE_ALLOC(ISL_Print("\n"));
   *slot = loc;
 }
 
 
 void FlowGraphAllocator::ConvertAllUses(LiveRange* range) {
   if (range->vreg() == kNoVirtualRegister) return;
 
   const Location loc = range->assigned_location();
   ASSERT(!loc.IsInvalid());
 
-  TRACE_ALLOC(OS::Print("range [%" Pd ", %" Pd ") "
+  TRACE_ALLOC(ISL_Print("range [%" Pd ", %" Pd ") "
                         "for v%" Pd " has been allocated to ",
                         range->Start(), range->End(), range->vreg()));
   TRACE_ALLOC(loc.Print());
-  TRACE_ALLOC(OS::Print(":\n"));
+  TRACE_ALLOC(ISL_Print(":\n"));
 
   for (UsePosition* use = range->first_use(); use != NULL; use = use->next()) {
     ConvertUseTo(use, loc);
   }
 
   // Add live registers at all safepoints for instructions with slow-path
   // code.
   if (loc.IsMachineRegister()) {
     for (SafepointPosition* safepoint = range->first_safepoint();
          safepoint != NULL;
@@ skipping 155 matching lines @@
 
 
 void FlowGraphAllocator::AllocateUnallocatedRanges() {
 #if defined(DEBUG)
   ASSERT(UnallocatedIsSorted());
 #endif
 
   while (!unallocated_.is_empty()) {
     LiveRange* range = unallocated_.RemoveLast();
     const intptr_t start = range->Start();
-    TRACE_ALLOC(OS::Print("Processing live range for v%" Pd " "
+    TRACE_ALLOC(ISL_Print("Processing live range for v%" Pd " "
                           "starting at %" Pd "\n",
                           range->vreg(),
                           start));
 
     // TODO(vegorov): eagerly spill liveranges without register uses.
     AdvanceActiveIntervals(start);
 
     if (!AllocateFreeRegister(range)) {
       if (intrinsic_mode_) {
         // No spilling when compiling intrinsics.
         // TODO(fschneider): Handle spilling in intrinsics. For now, the
         // IR has to be built so that there are enough free registers.
         UNREACHABLE();
       }
       AllocateAnyRegister(range);
     }
   }
 
   // All allocation decisions were done.
   ASSERT(unallocated_.is_empty());
 
   // Finish allocation.
   AdvanceActiveIntervals(kMaxPosition);
-  TRACE_ALLOC(OS::Print("Allocation completed\n"));
+  TRACE_ALLOC(ISL_Print("Allocation completed\n"));
 }
 
 
 bool FlowGraphAllocator::TargetLocationIsSpillSlot(LiveRange* range,
                                                    Location target) {
   if (target.IsStackSlot() ||
       target.IsDoubleStackSlot() ||
       target.IsConstant()) {
     ASSERT(GetLiveRange(range->vreg())->spill_slot().Equals(target));
     return true;
   }
   return false;
 }
 
 
 void FlowGraphAllocator::ConnectSplitSiblings(LiveRange* parent,
                                               BlockEntryInstr* source_block,
                                               BlockEntryInstr* target_block) {
-  TRACE_ALLOC(OS::Print("Connect v%" Pd " on the edge B%" Pd " -> B%" Pd "\n",
+  TRACE_ALLOC(ISL_Print("Connect v%" Pd " on the edge B%" Pd " -> B%" Pd "\n",
                         parent->vreg(),
                         source_block->block_id(),
                         target_block->block_id()));
   if (parent->next_sibling() == NULL) {
     // Nothing to connect. The whole range was allocated to the same location.
-    TRACE_ALLOC(OS::Print("range v%" Pd " has no siblings\n", parent->vreg()));
+    TRACE_ALLOC(ISL_Print("range v%" Pd " has no siblings\n", parent->vreg()));
     return;
   }
 
   const intptr_t source_pos = source_block->end_pos() - 1;
   ASSERT(IsInstructionEndPosition(source_pos));
 
   const intptr_t target_pos = target_block->start_pos();
 
   Location target;
   Location source;
@@ skipping 16 matching lines @@
       ASSERT(target.IsInvalid());
       target = range->assigned_location();
 #if defined(DEBUG)
       target_cover = range;
 #endif
     }
 
     range = range->next_sibling();
   }
 
-  TRACE_ALLOC(OS::Print("connecting v%" Pd " between [%" Pd ", %" Pd ") {%s} "
+  TRACE_ALLOC(ISL_Print("connecting v%" Pd " between [%" Pd ", %" Pd ") {%s} "
                         "to [%" Pd ", %" Pd ") {%s}\n",
                         parent->vreg(),
                         source_cover->Start(),
                         source_cover->End(),
                         source.Name(),
                         target_cover->Start(),
                         target_cover->End(),
                         target.Name()));
 
   // Siblings were allocated to the same register.
@@ skipping 16 matching lines @@
 
 void FlowGraphAllocator::ResolveControlFlow() {
   // Resolve linear control flow between touching split siblings
   // inside basic blocks.
   for (intptr_t vreg = 0; vreg < live_ranges_.length(); vreg++) {
     LiveRange* range = live_ranges_[vreg];
     if (range == NULL) continue;
 
     while (range->next_sibling() != NULL) {
       LiveRange* sibling = range->next_sibling();
-      TRACE_ALLOC(OS::Print("connecting [%" Pd ", %" Pd ") [",
+      TRACE_ALLOC(ISL_Print("connecting [%" Pd ", %" Pd ") [",
                             range->Start(), range->End()));
       TRACE_ALLOC(range->assigned_location().Print());
-      TRACE_ALLOC(OS::Print("] to [%" Pd ", %" Pd ") [",
+      TRACE_ALLOC(ISL_Print("] to [%" Pd ", %" Pd ") [",
                             sibling->Start(), sibling->End()));
       TRACE_ALLOC(sibling->assigned_location().Print());
-      TRACE_ALLOC(OS::Print("]\n"));
+      TRACE_ALLOC(ISL_Print("]\n"));
       if ((range->End() == sibling->Start()) &&
           !TargetLocationIsSpillSlot(range, sibling->assigned_location()) &&
           !range->assigned_location().Equals(sibling->assigned_location()) &&
           !IsBlockEntry(range->End())) {
         AddMoveAt(sibling->Start(),
                   sibling->assigned_location(),
                   range->assigned_location());
       }
       range = sibling;
     }
@@ skipping 110 matching lines @@
   DiscoverLoops();
 
   BuildLiveRanges();
 
   if (FLAG_print_ssa_liveness) {
     liveness_.Dump();
   }
 
   if (FLAG_print_ssa_liveranges) {
     const Function& function = flow_graph_.function();
-    OS::Print("-- [before ssa allocator] ranges [%s] ---------\n",
+    ISL_Print("-- [before ssa allocator] ranges [%s] ---------\n",
               function.ToFullyQualifiedCString());
     PrintLiveRanges();
-    OS::Print("----------------------------------------------\n");
+    ISL_Print("----------------------------------------------\n");
 
-    OS::Print("-- [before ssa allocator] ir [%s] -------------\n",
+    ISL_Print("-- [before ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     FlowGraphPrinter printer(flow_graph_, true);
     printer.PrintBlocks();
-    OS::Print("----------------------------------------------\n");
+    ISL_Print("----------------------------------------------\n");
   }
 
   PrepareForAllocation(Location::kRegister,
                        kNumberOfCpuRegisters,
                        unallocated_cpu_,
                        cpu_regs_,
                        blocked_cpu_registers_);
   AllocateUnallocatedRanges();
 
   cpu_spill_slot_count_ = spill_slots_.length();
@@ skipping 11 matching lines @@
   ResolveControlFlow();
 
   GraphEntryInstr* entry = block_order_[0]->AsGraphEntry();
   ASSERT(entry != NULL);
   intptr_t double_spill_slot_count = spill_slots_.length() * kDoubleSpillFactor;
   entry->set_spill_slot_count(cpu_spill_slot_count_ + double_spill_slot_count);
 
   if (FLAG_print_ssa_liveranges) {
     const Function& function = flow_graph_.function();
 
-    OS::Print("-- [after ssa allocator] ranges [%s] ---------\n",
+    ISL_Print("-- [after ssa allocator] ranges [%s] ---------\n",
               function.ToFullyQualifiedCString());
     PrintLiveRanges();
-    OS::Print("----------------------------------------------\n");
+    ISL_Print("----------------------------------------------\n");
 
-    OS::Print("-- [after ssa allocator] ir [%s] -------------\n",
+    ISL_Print("-- [after ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     FlowGraphPrinter printer(flow_graph_, true);
     printer.PrintBlocks();
-    OS::Print("----------------------------------------------\n");
+    ISL_Print("----------------------------------------------\n");
   }
 }
 
 
 }  // namespace dart