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Side by Side Diff: src/x64/assembler-x64-inl.h

Issue 90643003: Experimental implementation: Exposing SIMD instructions into JavaScript Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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192 void Assembler::emit_optional_rex_32(Register reg, XMMRegister base) { 192 void Assembler::emit_optional_rex_32(Register reg, XMMRegister base) {
193 byte rex_bits = (reg.code() & 0x8) >> 1 | (base.code() & 0x8) >> 3; 193 byte rex_bits = (reg.code() & 0x8) >> 1 | (base.code() & 0x8) >> 3;
194 if (rex_bits != 0) emit(0x40 | rex_bits); 194 if (rex_bits != 0) emit(0x40 | rex_bits);
195 } 195 }
196 196
197 197
198 void Assembler::emit_optional_rex_32(Register rm_reg) { 198 void Assembler::emit_optional_rex_32(Register rm_reg) {
199 if (rm_reg.high_bit()) emit(0x41); 199 if (rm_reg.high_bit()) emit(0x41);
200 } 200 }
201 201
202 void Assembler::emit_optional_rex_32(XMMRegister reg) {
203 byte rex_bits = (reg.code() & 0x8) >> 1;
204 if (rex_bits != 0) emit(0x40 | rex_bits);
205 }
202 206
203 void Assembler::emit_optional_rex_32(const Operand& op) { 207 void Assembler::emit_optional_rex_32(const Operand& op) {
204 if (op.rex_ != 0) emit(0x40 | op.rex_); 208 if (op.rex_ != 0) emit(0x40 | op.rex_);
205 } 209 }
206 210
207 211
208 Address Assembler::target_address_at(Address pc) { 212 Address Assembler::target_address_at(Address pc) {
209 return Memory::int32_at(pc) + pc + 4; 213 return Memory::int32_at(pc) + pc + 4;
210 } 214 }
211 215
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551 ASSERT(len_ == 1 || len_ == 2); 555 ASSERT(len_ == 1 || len_ == 2);
552 int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]); 556 int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]);
553 *p = disp; 557 *p = disp;
554 len_ += sizeof(int32_t); 558 len_ += sizeof(int32_t);
555 } 559 }
556 560
557 561
558 } } // namespace v8::internal 562 } } // namespace v8::internal
559 563
560 #endif // V8_X64_ASSEMBLER_X64_INL_H_ 564 #endif // V8_X64_ASSEMBLER_X64_INL_H_
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