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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_PPC_CONSTANTS_PPC_H_ | 5 #ifndef V8_PPC_CONSTANTS_PPC_H_ |
6 #define V8_PPC_CONSTANTS_PPC_H_ | 6 #define V8_PPC_CONSTANTS_PPC_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 | 10 |
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156 BCCTRX = 528 << 1 // Branch Conditional to Count Register | 156 BCCTRX = 528 << 1 // Branch Conditional to Count Register |
157 }; | 157 }; |
158 | 158 |
159 // Bits 9-1 or 10-1 | 159 // Bits 9-1 or 10-1 |
160 enum OpcodeExt2 { | 160 enum OpcodeExt2 { |
161 CMP = 0 << 1, | 161 CMP = 0 << 1, |
162 TW = 4 << 1, | 162 TW = 4 << 1, |
163 SUBFCX = 8 << 1, | 163 SUBFCX = 8 << 1, |
164 ADDCX = 10 << 1, | 164 ADDCX = 10 << 1, |
165 MULHWUX = 11 << 1, | 165 MULHWUX = 11 << 1, |
| 166 ISEL = 15 << 1, |
166 MFCR = 19 << 1, | 167 MFCR = 19 << 1, |
167 LWARX = 20 << 1, | 168 LWARX = 20 << 1, |
168 LDX = 21 << 1, | 169 LDX = 21 << 1, |
169 LWZX = 23 << 1, // load word zero w/ x-form | 170 LWZX = 23 << 1, // load word zero w/ x-form |
170 SLWX = 24 << 1, | 171 SLWX = 24 << 1, |
171 CNTLZWX = 26 << 1, | 172 CNTLZWX = 26 << 1, |
172 SLDX = 27 << 1, | 173 SLDX = 27 << 1, |
173 ANDX = 28 << 1, | 174 ANDX = 28 << 1, |
174 CMPL = 32 << 1, | 175 CMPL = 32 << 1, |
175 SUBFX = 40 << 1, | 176 SUBFX = 40 << 1, |
176 MFVSRD = 51 << 1, // Move From VSR Doubleword | 177 MFVSRD = 51 << 1, // Move From VSR Doubleword |
177 LDUX = 53 << 1, | 178 LDUX = 53 << 1, |
178 DCBST = 54 << 1, | 179 DCBST = 54 << 1, |
179 LWZUX = 55 << 1, // load word zero w/ update x-form | 180 LWZUX = 55 << 1, // load word zero w/ update x-form |
180 CNTLZDX = 58 << 1, | 181 CNTLZDX = 58 << 1, |
181 ANDCX = 60 << 1, | 182 ANDCX = 60 << 1, |
182 MULHWX = 75 << 1, | 183 MULHWX = 75 << 1, |
183 DCBF = 86 << 1, | 184 DCBF = 86 << 1, |
184 LBZX = 87 << 1, // load byte zero w/ x-form | 185 LBZX = 87 << 1, // load byte zero w/ x-form |
185 NEGX = 104 << 1, | 186 NEGX = 104 << 1, |
186 MFVSRWZ = 115 << 1, // Move From VSR Word And Zero | 187 MFVSRWZ = 115 << 1, // Move From VSR Word And Zero |
187 LBZUX = 119 << 1, // load byte zero w/ update x-form | 188 LBZUX = 119 << 1, // load byte zero w/ update x-form |
188 NORX = 124 << 1, | 189 NORX = 124 << 1, |
189 SUBFEX = 136 << 1, | 190 SUBFEX = 136 << 1, |
190 ADDEX = 138 << 1, | 191 ADDEX = 138 << 1, |
191 STDX = 149 << 1, | 192 STDX = 149 << 1, |
192 STWX = 151 << 1, // store word w/ x-form | 193 STWX = 151 << 1, // store word w/ x-form |
193 MTVSRD = 179 << 1, // Move To VSR Doubleword | 194 MTVSRD = 179 << 1, // Move To VSR Doubleword |
194 STDUX = 181 << 1, | 195 STDUX = 181 << 1, |
195 STWUX = 183 << 1, // store word w/ update x-form | 196 STWUX = 183 << 1, // store word w/ update x-form |
196 /* | 197 /* |
197 MTCRF | 198 MTCRF |
198 MTMSR | 199 MTMSR |
199 STWCXx | 200 STWCXx |
200 SUBFZEX | 201 SUBFZEX |
201 */ | 202 */ |
202 ADDZEX = 202 << 1, // Add to Zero Extended | 203 ADDZEX = 202 << 1, // Add to Zero Extended |
203 /* | 204 /* |
204 MTSR | 205 MTSR |
205 */ | 206 */ |
206 MTVSRWA = 211 << 1, // Move To VSR Word Algebraic | 207 MTVSRWA = 211 << 1, // Move To VSR Word Algebraic |
207 STBX = 215 << 1, // store byte w/ x-form | 208 STBX = 215 << 1, // store byte w/ x-form |
208 MULLD = 233 << 1, // Multiply Low Double Word | 209 MULLD = 233 << 1, // Multiply Low Double Word |
209 MULLW = 235 << 1, // Multiply Low Word | 210 MULLW = 235 << 1, // Multiply Low Word |
210 MTVSRWZ = 243 << 1, // Move To VSR Word And Zero | 211 MTVSRWZ = 243 << 1, // Move To VSR Word And Zero |
211 STBUX = 247 << 1, // store byte w/ update x-form | 212 STBUX = 247 << 1, // store byte w/ update x-form |
212 ADDX = 266 << 1, // Add | 213 ADDX = 266 << 1, // Add |
213 LHZX = 279 << 1, // load half-word zero w/ x-form | 214 LHZX = 279 << 1, // load half-word zero w/ x-form |
214 LHZUX = 311 << 1, // load half-word zero w/ update x-form | 215 LHZUX = 311 << 1, // load half-word zero w/ update x-form |
| 216 LWAX = 341 << 1, // load word algebraic w/ x-form |
215 LHAX = 343 << 1, // load half-word algebraic w/ x-form | 217 LHAX = 343 << 1, // load half-word algebraic w/ x-form |
216 LHAUX = 375 << 1, // load half-word algebraic w/ update x-form | 218 LHAUX = 375 << 1, // load half-word algebraic w/ update x-form |
217 XORX = 316 << 1, // Exclusive OR | 219 XORX = 316 << 1, // Exclusive OR |
218 MFSPR = 339 << 1, // Move from Special-Purpose-Register | 220 MFSPR = 339 << 1, // Move from Special-Purpose-Register |
219 STHX = 407 << 1, // store half-word w/ x-form | 221 STHX = 407 << 1, // store half-word w/ x-form |
| 222 ORC = 412 << 1, // Or with Complement |
220 STHUX = 439 << 1, // store half-word w/ update x-form | 223 STHUX = 439 << 1, // store half-word w/ update x-form |
221 ORX = 444 << 1, // Or | 224 ORX = 444 << 1, // Or |
| 225 DIVDU = 457 << 1, // Divide Double Word Unsigned |
| 226 DIVWU = 459 << 1, // Divide Word Unsigned |
222 MTSPR = 467 << 1, // Move to Special-Purpose-Register | 227 MTSPR = 467 << 1, // Move to Special-Purpose-Register |
223 DIVD = 489 << 1, // Divide Double Word | 228 DIVD = 489 << 1, // Divide Double Word |
224 DIVW = 491 << 1, // Divide Word | 229 DIVW = 491 << 1, // Divide Word |
225 | 230 |
226 // Below represent bits 10-1 (any value >= 512) | 231 // Below represent bits 10-1 (any value >= 512) |
227 LFSX = 535 << 1, // load float-single w/ x-form | 232 LFSX = 535 << 1, // load float-single w/ x-form |
228 SRWX = 536 << 1, // Shift Right Word | 233 SRWX = 536 << 1, // Shift Right Word |
229 SRDX = 539 << 1, // Shift Right Double Word | 234 SRDX = 539 << 1, // Shift Right Double Word |
230 LFSUX = 567 << 1, // load float-single w/ update x-form | 235 LFSUX = 567 << 1, // load float-single w/ update x-form |
231 SYNC = 598 << 1, // Synchronize | 236 SYNC = 598 << 1, // Synchronize |
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260 // Bits 10-1 | 265 // Bits 10-1 |
261 FCMPU = 0 << 1, // Floating Compare Unordered | 266 FCMPU = 0 << 1, // Floating Compare Unordered |
262 FRSP = 12 << 1, // Floating-Point Rounding | 267 FRSP = 12 << 1, // Floating-Point Rounding |
263 FCTIW = 14 << 1, // Floating Convert to Integer Word X-form | 268 FCTIW = 14 << 1, // Floating Convert to Integer Word X-form |
264 FCTIWZ = 15 << 1, // Floating Convert to Integer Word with Round to Zero | 269 FCTIWZ = 15 << 1, // Floating Convert to Integer Word with Round to Zero |
265 FNEG = 40 << 1, // Floating Negate | 270 FNEG = 40 << 1, // Floating Negate |
266 MCRFS = 64 << 1, // Move to Condition Register from FPSCR | 271 MCRFS = 64 << 1, // Move to Condition Register from FPSCR |
267 FMR = 72 << 1, // Floating Move Register | 272 FMR = 72 << 1, // Floating Move Register |
268 MTFSFI = 134 << 1, // Move to FPSCR Field Immediate | 273 MTFSFI = 134 << 1, // Move to FPSCR Field Immediate |
269 FABS = 264 << 1, // Floating Absolute Value | 274 FABS = 264 << 1, // Floating Absolute Value |
| 275 FRIN = 392 << 1, // Floating Round to Integer Nearest |
| 276 FRIZ = 424 << 1, // Floating Round to Integer Toward Zero |
| 277 FRIP = 456 << 1, // Floating Round to Integer Plus |
270 FRIM = 488 << 1, // Floating Round to Integer Minus | 278 FRIM = 488 << 1, // Floating Round to Integer Minus |
271 MFFS = 583 << 1, // move from FPSCR x-form | 279 MFFS = 583 << 1, // move from FPSCR x-form |
272 MTFSF = 711 << 1, // move to FPSCR fields XFL-form | 280 MTFSF = 711 << 1, // move to FPSCR fields XFL-form |
273 FCFID = 846 << 1, // Floating convert from integer doubleword | 281 FCFID = 846 << 1, // Floating convert from integer doubleword |
274 FCTID = 814 << 1, // Floating convert from integer doubleword | 282 FCTID = 814 << 1, // Floating convert from integer doubleword |
275 FCTIDZ = 815 << 1 // Floating convert from integer doubleword | 283 FCTIDZ = 815 << 1 // Floating convert from integer doubleword |
276 }; | 284 }; |
277 | 285 |
278 enum OpcodeExt5 { | 286 enum OpcodeExt5 { |
279 // Bits 4-2 | 287 // Bits 4-2 |
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327 kExt5OpcodeMask = 0x3 << 2, | 335 kExt5OpcodeMask = 0x3 << 2, |
328 kBOMask = 0x1f << 21, | 336 kBOMask = 0x1f << 21, |
329 kBIMask = 0x1F << 16, | 337 kBIMask = 0x1F << 16, |
330 kBDMask = 0x14 << 2, | 338 kBDMask = 0x14 << 2, |
331 kAAMask = 0x01 << 1, | 339 kAAMask = 0x01 << 1, |
332 kLKMask = 0x01, | 340 kLKMask = 0x01, |
333 kRCMask = 0x01, | 341 kRCMask = 0x01, |
334 kTOMask = 0x1f << 21 | 342 kTOMask = 0x1f << 21 |
335 }; | 343 }; |
336 | 344 |
337 // the following is to differentiate different faked opcodes for | |
338 // the BOGUS PPC instruction we invented (when bit 25 is 0) or to mark | |
339 // different stub code (when bit 25 is 1) | |
340 // - use primary opcode 1 for undefined instruction | |
341 // - use bit 25 to indicate whether the opcode is for fake-arm | |
342 // instr or stub-marker | |
343 // - use the least significant 6-bit to indicate FAKE_OPCODE_T or | |
344 // MARKER_T | |
345 #define FAKE_OPCODE 1 << 26 | |
346 #define MARKER_SUBOPCODE_BIT 25 | |
347 #define MARKER_SUBOPCODE 1 << MARKER_SUBOPCODE_BIT | |
348 #define FAKER_SUBOPCODE 0 << MARKER_SUBOPCODE_BIT | |
349 | |
350 enum FAKE_OPCODE_T { | |
351 fBKPT = 14, | |
352 fLastFaker // can't be more than 128 (2^^7) | |
353 }; | |
354 #define FAKE_OPCODE_HIGH_BIT 7 // fake opcode has to fall into bit 0~7 | |
355 #define F_NEXT_AVAILABLE_STUB_MARKER 369 // must be less than 2^^9 (512) | |
356 #define STUB_MARKER_HIGH_BIT 9 // stub marker has to fall into bit 0~9 | |
357 // ----------------------------------------------------------------------------- | 345 // ----------------------------------------------------------------------------- |
358 // Addressing modes and instruction variants. | 346 // Addressing modes and instruction variants. |
359 | 347 |
360 // Overflow Exception | 348 // Overflow Exception |
361 enum OEBit { | 349 enum OEBit { |
362 SetOE = 1 << 10, // Set overflow exception | 350 SetOE = 1 << 10, // Set overflow exception |
363 LeaveOE = 0 << 10 // No overflow exception | 351 LeaveOE = 0 << 10 // No overflow exception |
364 }; | 352 }; |
365 | 353 |
366 // Record bit | 354 // Record bit |
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404 // Special Software Interrupt codes when used in the presence of the PPC | 392 // Special Software Interrupt codes when used in the presence of the PPC |
405 // simulator. | 393 // simulator. |
406 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for | 394 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for |
407 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. | 395 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. |
408 enum SoftwareInterruptCodes { | 396 enum SoftwareInterruptCodes { |
409 // transition to C code | 397 // transition to C code |
410 kCallRtRedirected = 0x10, | 398 kCallRtRedirected = 0x10, |
411 // break point | 399 // break point |
412 kBreakpoint = 0x821008, // bits23-0 of 0x7d821008 = twge r2, r2 | 400 kBreakpoint = 0x821008, // bits23-0 of 0x7d821008 = twge r2, r2 |
413 // stop | 401 // stop |
414 kStopCode = 1 << 23, | 402 kStopCode = 1 << 23 |
415 // info | |
416 kInfo = 0x9ff808 // bits23-0 of 0x7d9ff808 = twge r31, r31 | |
417 }; | 403 }; |
418 const uint32_t kStopCodeMask = kStopCode - 1; | 404 const uint32_t kStopCodeMask = kStopCode - 1; |
419 const uint32_t kMaxStopCode = kStopCode - 1; | 405 const uint32_t kMaxStopCode = kStopCode - 1; |
420 const int32_t kDefaultStopCode = -1; | 406 const int32_t kDefaultStopCode = -1; |
421 | 407 |
422 // FP rounding modes. | 408 // FP rounding modes. |
423 enum FPRoundingMode { | 409 enum FPRoundingMode { |
424 RN = 0, // Round to Nearest. | 410 RN = 0, // Round to Nearest. |
425 RZ = 1, // Round towards zero. | 411 RZ = 1, // Round towards zero. |
426 RP = 2, // Round towards Plus Infinity. | 412 RP = 2, // Round towards Plus Infinity. |
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591 // Lookup the register number for the name provided. | 577 // Lookup the register number for the name provided. |
592 static int Number(const char* name); | 578 static int Number(const char* name); |
593 | 579 |
594 private: | 580 private: |
595 static const char* names_[kNumFPRegisters]; | 581 static const char* names_[kNumFPRegisters]; |
596 }; | 582 }; |
597 } | 583 } |
598 } // namespace v8::internal | 584 } // namespace v8::internal |
599 | 585 |
600 #endif // V8_PPC_CONSTANTS_PPC_H_ | 586 #endif // V8_PPC_CONSTANTS_PPC_H_ |
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