Contribution of PowerPC port (continuation of 422063005) - PPC dir update

src/ppc/constants-ppc.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_PPC_CONSTANTS_PPC_H_
 #define V8_PPC_CONSTANTS_PPC_H_
 
 namespace v8 {
 namespace internal {
 
@@ skipping 145 matching lines @@
   BCCTRX = 528 << 1   // Branch Conditional to Count Register
 };
 
 // Bits 9-1 or 10-1
 enum OpcodeExt2 {
   CMP = 0 << 1,
   TW = 4 << 1,
   SUBFCX = 8 << 1,
   ADDCX = 10 << 1,
   MULHWUX = 11 << 1,
+  ISEL = 15 << 1,
   MFCR = 19 << 1,
   LWARX = 20 << 1,
   LDX = 21 << 1,
   LWZX = 23 << 1,  // load word zero w/ x-form
   SLWX = 24 << 1,
   CNTLZWX = 26 << 1,
   SLDX = 27 << 1,
   ANDX = 28 << 1,
   CMPL = 32 << 1,
   SUBFX = 40 << 1,
   MFVSRD = 51 << 1,  // Move From VSR Doubleword
   LDUX = 53 << 1,
   DCBST = 54 << 1,
   LWZUX = 55 << 1,  // load word zero w/ update x-form
   CNTLZDX = 58 << 1,
   ANDCX = 60 << 1,
   MULHWX = 75 << 1,
   DCBF = 86 << 1,
   LBZX = 87 << 1,  // load byte zero w/ x-form
   NEGX = 104 << 1,
   MFVSRWZ = 115 << 1,  // Move From VSR Word And Zero
   LBZUX = 119 << 1,    // load byte zero w/ update x-form
   NORX = 124 << 1,
   SUBFEX = 136 << 1,
   ADDEX = 138 << 1,
   STDX = 149 << 1,
   STWX = 151 << 1,    // store word w/ x-form
   MTVSRD = 179 << 1,  // Move To VSR Doubleword
   STDUX = 181 << 1,
-  STWUX = 183 << 1,  // store word w/ update x-form
-                     /*
-    MTCRF
-    MTMSR
-    STWCXx
-    SUBFZEX
-  */
-  ADDZEX = 202 << 1,  // Add to Zero Extended
-                      /*
-    MTSR
-  */
+  STWUX = 183 << 1,    // store word w/ update x-form
+                       /*
+      MTCRF
+      MTMSR
+      STWCXx
+      SUBFZEX
+    */
+  ADDZEX = 202 << 1,   // Add to Zero Extended
+                       /*
+     MTSR
+   */
   MTVSRWA = 211 << 1,  // Move To VSR Word Algebraic
   STBX = 215 << 1,     // store byte w/ x-form
   MULLD = 233 << 1,    // Multiply Low Double Word
   MULLW = 235 << 1,    // Multiply Low Word
   MTVSRWZ = 243 << 1,  // Move To VSR Word And Zero
   STBUX = 247 << 1,    // store byte w/ update x-form
   ADDX = 266 << 1,     // Add
   LHZX = 279 << 1,     // load half-word zero w/ x-form
   LHZUX = 311 << 1,    // load half-word zero w/ update x-form
+  LWAX = 341 << 1,     // load word algebraic w/ x-form
   LHAX = 343 << 1,     // load half-word algebraic w/ x-form
   LHAUX = 375 << 1,    // load half-word algebraic w/ update x-form
   XORX = 316 << 1,     // Exclusive OR
   MFSPR = 339 << 1,    // Move from Special-Purpose-Register
   STHX = 407 << 1,     // store half-word w/ x-form
+  ORC = 412 << 1,      // Or with Complement
   STHUX = 439 << 1,    // store half-word w/ update x-form
   ORX = 444 << 1,      // Or
+  DIVDU = 457 << 1,    // Divide Double Word Unsigned
+  DIVWU = 459 << 1,    // Divide Word Unsigned
   MTSPR = 467 << 1,    // Move to Special-Purpose-Register
   DIVD = 489 << 1,     // Divide Double Word
   DIVW = 491 << 1,     // Divide Word
 
   // Below represent bits 10-1  (any value >= 512)
   LFSX = 535 << 1,    // load float-single w/ x-form
   SRWX = 536 << 1,    // Shift Right Word
   SRDX = 539 << 1,    // Shift Right Double Word
   LFSUX = 567 << 1,   // load float-single w/ update x-form
   SYNC = 598 << 1,    // Synchronize
@@ skipping 28 matching lines @@
   // Bits 10-1
   FCMPU = 0 << 1,     // Floating Compare Unordered
   FRSP = 12 << 1,     // Floating-Point Rounding
   FCTIW = 14 << 1,    // Floating Convert to Integer Word X-form
   FCTIWZ = 15 << 1,   // Floating Convert to Integer Word with Round to Zero
   FNEG = 40 << 1,     // Floating Negate
   MCRFS = 64 << 1,    // Move to Condition Register from FPSCR
   FMR = 72 << 1,      // Floating Move Register
   MTFSFI = 134 << 1,  // Move to FPSCR Field Immediate
   FABS = 264 << 1,    // Floating Absolute Value
+  FRIN = 392 << 1,    // Floating Round to Integer Nearest
+  FRIZ = 424 << 1,    // Floating Round to Integer Toward Zero
+  FRIP = 456 << 1,    // Floating Round to Integer Plus
   FRIM = 488 << 1,    // Floating Round to Integer Minus
   MFFS = 583 << 1,    // move from FPSCR x-form
   MTFSF = 711 << 1,   // move to FPSCR fields XFL-form
   FCFID = 846 << 1,   // Floating convert from integer doubleword
   FCTID = 814 << 1,   // Floating convert from integer doubleword
   FCTIDZ = 815 << 1   // Floating convert from integer doubleword
 };
 
 enum OpcodeExt5 {
   // Bits 4-2
@@ skipping 47 matching lines @@
   kExt5OpcodeMask = 0x3 << 2,
   kBOMask = 0x1f << 21,
   kBIMask = 0x1F << 16,
   kBDMask = 0x14 << 2,
   kAAMask = 0x01 << 1,
   kLKMask = 0x01,
   kRCMask = 0x01,
   kTOMask = 0x1f << 21
 };
 
-// the following is to differentiate different faked opcodes for
-// the BOGUS PPC instruction we invented (when bit 25 is 0) or to mark
-// different stub code (when bit 25 is 1)
-//   - use primary opcode 1 for undefined instruction
-//   - use bit 25 to indicate whether the opcode is for fake-arm
-//     instr or stub-marker
-//   - use the least significant 6-bit to indicate FAKE_OPCODE_T or
-//     MARKER_T
-#define FAKE_OPCODE 1 << 26
-#define MARKER_SUBOPCODE_BIT 25
-#define MARKER_SUBOPCODE 1 << MARKER_SUBOPCODE_BIT
-#define FAKER_SUBOPCODE 0 << MARKER_SUBOPCODE_BIT
-
-enum FAKE_OPCODE_T {
-  fBKPT = 14,
-  fLastFaker  // can't be more than 128 (2^^7)
-};
-#define FAKE_OPCODE_HIGH_BIT 7  // fake opcode has to fall into bit 0~7
-#define F_NEXT_AVAILABLE_STUB_MARKER 369  // must be less than 2^^9 (512)
-#define STUB_MARKER_HIGH_BIT 9  // stub marker has to fall into bit 0~9
 // -----------------------------------------------------------------------------
 // Addressing modes and instruction variants.
 
 // Overflow Exception
 enum OEBit {
   SetOE = 1 << 10,   // Set overflow exception
   LeaveOE = 0 << 10  // No overflow exception
 };
 
 // Record bit
@@ skipping 37 matching lines @@
 // Special Software Interrupt codes when used in the presence of the PPC
 // simulator.
 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
 enum SoftwareInterruptCodes {
   // transition to C code
   kCallRtRedirected = 0x10,
   // break point
   kBreakpoint = 0x821008,  // bits23-0 of 0x7d821008 = twge r2, r2
   // stop
-  kStopCode = 1 << 23,
-  // info
-  kInfo = 0x9ff808  // bits23-0 of 0x7d9ff808 = twge r31, r31
+  kStopCode = 1 << 23
 };
 const uint32_t kStopCodeMask = kStopCode - 1;
 const uint32_t kMaxStopCode = kStopCode - 1;
 const int32_t kDefaultStopCode = -1;
 
 // FP rounding modes.
 enum FPRoundingMode {
   RN = 0,  // Round to Nearest.
   RZ = 1,  // Round towards zero.
   RP = 2,  // Round towards Plus Infinity.
@@ skipping 164 matching lines @@
   // Lookup the register number for the name provided.
   static int Number(const char* name);
 
  private:
   static const char* names_[kNumFPRegisters];
 };
 }
 }  // namespace v8::internal
 
 #endif  // V8_PPC_CONSTANTS_PPC_H_