Contribution of PowerPC port (continuation of 422063005) - PPC dir update

src/ppc/assembler-ppc.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 59 matching lines @@
 #if V8_TARGET_ARCH_PPC64
   if (cpu.part() == base::CPU::PPC_POWER8) {
     supported_ |= (1u << FPR_GPR_MOV);
   }
 #endif
   if (cpu.part() == base::CPU::PPC_POWER6 ||
       cpu.part() == base::CPU::PPC_POWER7 ||
       cpu.part() == base::CPU::PPC_POWER8) {
     supported_ |= (1u << LWSYNC);
   }
+  if (cpu.part() == base::CPU::PPC_POWER7 ||
+      cpu.part() == base::CPU::PPC_POWER8) {
+    supported_ |= (1u << ISELECT);
+  }
 #if V8_OS_LINUX
   if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
     // Assume support
     supported_ |= (1u << FPU);
   }
 #elif V8_OS_AIX
   // Assume support FP support and default cache line size
   supported_ |= (1u << FPU);
 #endif
 #else  // Simulator
   supported_ |= (1u << FPU);
   supported_ |= (1u << LWSYNC);
+  supported_ |= (1u << ISELECT);
 #if V8_TARGET_ARCH_PPC64
   supported_ |= (1u << FPR_GPR_MOV);
 #endif
 #endif
 }
 
 
 void CpuFeatures::PrintTarget() {
   const char* ppc_arch = NULL;
 
@@ skipping 108 matching lines @@
 MemOperand::MemOperand(Register ra, Register rb) {
   ra_ = ra;
   rb_ = rb;
   offset_ = 0;
 }
 
 
 // -----------------------------------------------------------------------------
 // Specific instructions, constants, and masks.
 
-// Spare buffer.
-static const int kMinimalBufferSize = 4 * KB;
-
 
 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
     : AssemblerBase(isolate, buffer, buffer_size),
       recorded_ast_id_(TypeFeedbackId::None()),
 #if V8_OOL_CONSTANT_POOL
       constant_pool_builder_(),
 #endif
       positions_recorder_(this) {
   reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
 
@@ skipping 182 matching lines @@
   } else if ((instr & ~kImm26Mask) == 0) {
     // Emitted link to a label, not part of a branch (regexp PushBacktrack).
     if (instr == 0) {
       return kEndOfChain;
     } else {
       int32_t imm26 = SIGN_EXT_IMM26(instr);
       return (imm26 + pos);
     }
   }
 
-  PPCPORT_UNIMPLEMENTED();
   DCHECK(false);
   return -1;
 }
 
 
 void Assembler::target_at_put(int pos, int target_pos) {
   Instr instr = instr_at(pos);
   int opcode = instr & kOpcodeMask;
 
   // check which type of branch this is 16 or 26 bit offset
   if (BX == opcode) {
     int imm26 = target_pos - pos;
-    DCHECK((imm26 & (kAAMask | kLKMask)) == 0);
-    instr &= ((~kImm26Mask) | kAAMask | kLKMask);
-    DCHECK(is_int26(imm26));
-    instr_at_put(pos, instr | (imm26 & kImm26Mask));
+    DCHECK(is_int26(imm26) && (imm26 & (kAAMask | kLKMask)) == 0);
+    if (imm26 == kInstrSize && !(instr & kLKMask)) {
+      // Branch to next instr without link.
+      instr = ORI;  // nop: ori, 0,0,0
+    } else {
+      instr &= ((~kImm26Mask) | kAAMask | kLKMask);
+      instr |= (imm26 & kImm26Mask);
+    }
+    instr_at_put(pos, instr);
     return;
   } else if (BCX == opcode) {
     int imm16 = target_pos - pos;
-    DCHECK((imm16 & (kAAMask | kLKMask)) == 0);
-    instr &= ((~kImm16Mask) | kAAMask | kLKMask);
-    DCHECK(is_int16(imm16));
-    instr_at_put(pos, instr | (imm16 & kImm16Mask));
+    DCHECK(is_int16(imm16) && (imm16 & (kAAMask | kLKMask)) == 0);
+    if (imm16 == kInstrSize && !(instr & kLKMask)) {
+      // Branch to next instr without link.
+      instr = ORI;  // nop: ori, 0,0,0
+    } else {
+      instr &= ((~kImm16Mask) | kAAMask | kLKMask);
+      instr |= (imm16 & kImm16Mask);
+    }
+    instr_at_put(pos, instr);
     return;
   } else if ((instr & ~kImm26Mask) == 0) {
     DCHECK(target_pos == kEndOfChain || target_pos >= 0);
     // Emitted link to a label, not part of a branch (regexp PushBacktrack).
     // Load the position of the label relative to the generated code object
     // pointer in a register.
 
     Register dst = r3;  // we assume r3 for now
     DCHECK(IsNop(instr_at(pos + kInstrSize)));
     uint32_t target = target_pos + (Code::kHeaderSize - kHeapObjectTag);
@@ skipping 392 matching lines @@
 
 
 // Multiply low word
 void Assembler::mullw(Register dst, Register src1, Register src2, OEBit o,
                       RCBit r) {
   xo_form(EXT2 | MULLW, dst, src1, src2, o, r);
 }
 
 
 // Multiply hi word
-void Assembler::mulhw(Register dst, Register src1, Register src2, OEBit o,
-                      RCBit r) {
-  xo_form(EXT2 | MULHWX, dst, src1, src2, o, r);
+void Assembler::mulhw(Register dst, Register src1, Register src2, RCBit r) {
+  xo_form(EXT2 | MULHWX, dst, src1, src2, LeaveOE, r);
 }
 
 
+// Multiply hi word unsigned
+void Assembler::mulhwu(Register dst, Register src1, Register src2, RCBit r) {
+  xo_form(EXT2 | MULHWUX, dst, src1, src2, LeaveOE, r);
+}
+
+
 // Divide word
 void Assembler::divw(Register dst, Register src1, Register src2, OEBit o,
                      RCBit r) {
   xo_form(EXT2 | DIVW, dst, src1, src2, o, r);
 }
 
 
+// Divide word unsigned
+void Assembler::divwu(Register dst, Register src1, Register src2, OEBit o,
+                      RCBit r) {
+  xo_form(EXT2 | DIVWU, dst, src1, src2, o, r);
+}
+
+
 void Assembler::addi(Register dst, Register src, const Operand& imm) {
   DCHECK(!src.is(r0));  // use li instead to show intent
   d_form(ADDI, dst, src, imm.imm_, true);
 }
 
 
 void Assembler::addis(Register dst, Register src, const Operand& imm) {
   DCHECK(!src.is(r0));  // use lis instead to show intent
   d_form(ADDIS, dst, src, imm.imm_, true);
 }
@@ skipping 32 matching lines @@
 void Assembler::oris(Register dst, Register src, const Operand& imm) {
   d_form(ORIS, src, dst, imm.imm_, false);
 }
 
 
 void Assembler::orx(Register dst, Register src1, Register src2, RCBit rc) {
   x_form(EXT2 | ORX, dst, src1, src2, rc);
 }
 
 
+void Assembler::orc(Register dst, Register src1, Register src2, RCBit rc) {
+  x_form(EXT2 | ORC, dst, src1, src2, rc);
+}
+
+
 void Assembler::cmpi(Register src1, const Operand& src2, CRegister cr) {
   intptr_t imm16 = src2.imm_;
 #if V8_TARGET_ARCH_PPC64
   int L = 1;
 #else
   int L = 0;
 #endif
   DCHECK(is_int16(imm16));
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   imm16 &= kImm16Mask;
@@ skipping 68 matching lines @@
 
 
 void Assembler::cmplw(Register src1, Register src2, CRegister cr) {
   int L = 0;
   DCHECK(cr.code() >= 0 && cr.code() <= 7);
   emit(EXT2 | CMPL | cr.code() * B23 | L * B21 | src1.code() * B16 |
        src2.code() * B11);
 }
 
 
+void Assembler::isel(Register rt, Register ra, Register rb, int cb) {
+  emit(EXT2 | ISEL | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
+       cb * B6);
+}
+
+
 // Pseudo op - load immediate
 void Assembler::li(Register dst, const Operand& imm) {
   d_form(ADDI, dst, r0, imm.imm_, true);
 }
 
 
 void Assembler::lis(Register dst, const Operand& imm) {
   d_form(ADDIS, dst, r0, imm.imm_, true);
 }
 
@@ skipping 46 matching lines @@
 
 void Assembler::lhzux(Register rt, const MemOperand& src) {
   Register ra = src.ra();
   Register rb = src.rb();
   DCHECK(!ra.is(r0));
   emit(EXT2 | LHZUX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
        LeaveRC);
 }
 
 
+void Assembler::lhax(Register rt, const MemOperand& src) {
+  Register ra = src.ra();
+  Register rb = src.rb();
+  DCHECK(!ra.is(r0));
+  emit(EXT2 | LHAX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
+}
+
+
 void Assembler::lwz(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(LWZ, dst, src.ra(), src.offset(), true);
 }
 
 
 void Assembler::lwzu(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(LWZU, dst, src.ra(), src.offset(), true);
 }
@@ skipping 10 matching lines @@
 
 void Assembler::lwzux(Register rt, const MemOperand& src) {
   Register ra = src.ra();
   Register rb = src.rb();
   DCHECK(!ra.is(r0));
   emit(EXT2 | LWZUX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
        LeaveRC);
 }
 
 
+void Assembler::lha(Register dst, const MemOperand& src) {
+  DCHECK(!src.ra_.is(r0));
+  d_form(LHA, dst, src.ra(), src.offset(), true);
+}
+
+
 void Assembler::lwa(Register dst, const MemOperand& src) {
 #if V8_TARGET_ARCH_PPC64
   int offset = src.offset();
   DCHECK(!src.ra_.is(r0));
   DCHECK(!(offset & 3) && is_int16(offset));
   offset = kImm16Mask & offset;
   emit(LD | dst.code() * B21 | src.ra().code() * B16 | offset | 2);
 #else
   lwz(dst, src);
 #endif
 }
 
 
+void Assembler::lwax(Register rt, const MemOperand& src) {
+#if V8_TARGET_ARCH_PPC64
+  Register ra = src.ra();
+  Register rb = src.rb();
+  DCHECK(!ra.is(r0));
+  emit(EXT2 | LWAX | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
+#else
+  lwzx(rt, src);
+#endif
+}
+
+
 void Assembler::stb(Register dst, const MemOperand& src) {
   DCHECK(!src.ra_.is(r0));
   d_form(STB, dst, src.ra(), src.offset(), true);
 }
 
 
 void Assembler::stbx(Register rs, const MemOperand& src) {
   Register ra = src.ra();
   Register rb = src.rb();
   DCHECK(!ra.is(r0));
@@ skipping 68 matching lines @@
 void Assembler::extsb(Register rs, Register ra, RCBit rc) {
   emit(EXT2 | EXTSB | ra.code() * B21 | rs.code() * B16 | rc);
 }
 
 
 void Assembler::extsh(Register rs, Register ra, RCBit rc) {
   emit(EXT2 | EXTSH | ra.code() * B21 | rs.code() * B16 | rc);
 }
 
 
+void Assembler::extsw(Register rs, Register ra, RCBit rc) {
+#if V8_TARGET_ARCH_PPC64
+  emit(EXT2 | EXTSW | ra.code() * B21 | rs.code() * B16 | rc);
+#else
+  // nop on 32-bit
+  DCHECK(rs.is(ra) && rc == LeaveRC);
+#endif
+}
+
+
 void Assembler::neg(Register rt, Register ra, OEBit o, RCBit r) {
   emit(EXT2 | NEGX | rt.code() * B21 | ra.code() * B16 | o | r);
 }
 
 
 void Assembler::andc(Register dst, Register src1, Register src2, RCBit rc) {
   x_form(EXT2 | ANDCX, dst, src1, src2, rc);
 }
 
 
@@ skipping 155 matching lines @@
 void Assembler::rotrdi(Register ra, Register rs, int sh, RCBit r) {
   rldicl(ra, rs, 64 - sh, 0, r);
 }
 
 
 void Assembler::cntlzd_(Register ra, Register rs, RCBit rc) {
   x_form(EXT2 | CNTLZDX, ra, rs, r0, rc);
 }
 
 
-void Assembler::extsw(Register rs, Register ra, RCBit rc) {
-  emit(EXT2 | EXTSW | ra.code() * B21 | rs.code() * B16 | rc);
-}
-
-
 void Assembler::mulld(Register dst, Register src1, Register src2, OEBit o,
                       RCBit r) {
   xo_form(EXT2 | MULLD, dst, src1, src2, o, r);
 }
 
 
 void Assembler::divd(Register dst, Register src1, Register src2, OEBit o,
                      RCBit r) {
   xo_form(EXT2 | DIVD, dst, src1, src2, o, r);
 }
+
+
+void Assembler::divdu(Register dst, Register src1, Register src2, OEBit o,
+                      RCBit r) {
+  xo_form(EXT2 | DIVDU, dst, src1, src2, o, r);
+}
 #endif
 
 
-void Assembler::fake_asm(enum FAKE_OPCODE_T fopcode) {
-  DCHECK(fopcode < fLastFaker);
-  emit(FAKE_OPCODE | FAKER_SUBOPCODE | fopcode);
-}
-
-
-void Assembler::marker_asm(int mcode) {
-  if (::v8::internal::FLAG_trace_sim_stubs) {
-    DCHECK(mcode < F_NEXT_AVAILABLE_STUB_MARKER);
-    emit(FAKE_OPCODE | MARKER_SUBOPCODE | mcode);
-  }
-}
-
-
 // Function descriptor for AIX.
 // Code address skips the function descriptor "header".
 // TOC and static chain are ignored and set to 0.
 void Assembler::function_descriptor() {
 #if ABI_USES_FUNCTION_DESCRIPTORS
   DCHECK(pc_offset() == 0);
   RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
   emit_ptr(reinterpret_cast<uintptr_t>(pc_) + 3 * kPointerSize);
   emit_ptr(0);
   emit_ptr(0);
@@ skipping 109 matching lines @@
 // and only use the generic version when we require a fixed sequence
 void Assembler::mov(Register dst, const Operand& src) {
   intptr_t value = src.immediate();
   bool canOptimize;
   RelocInfo rinfo(pc_, src.rmode_, value, NULL);
 
   if (src.must_output_reloc_info(this)) {
     RecordRelocInfo(rinfo);
   }
 
-  canOptimize =
-      !(src.must_output_reloc_info(this) || is_trampoline_pool_blocked());
+  canOptimize = !(src.must_output_reloc_info(this) ||
+                  (is_trampoline_pool_blocked() && !is_int16(value)));
 
 #if V8_OOL_CONSTANT_POOL
   if (use_constant_pool_for_mov(src, canOptimize)) {
     DCHECK(is_ool_constant_pool_available());
     ConstantPoolAddEntry(rinfo);
 #if V8_TARGET_ARCH_PPC64
     BlockTrampolinePoolScope block_trampoline_pool(this);
     // We are forced to use 2 instruction sequence since the constant
     // pool pointer is tagged.
     li(dst, Operand::Zero());
@@ skipping 175 matching lines @@
     bind(&skip);
   } else {
     bkpt(0);
   }
 }
 
 
 void Assembler::bkpt(uint32_t imm16) { emit(0x7d821008); }
 
 
-void Assembler::info(const char* msg, Condition cond, int32_t code,
-                     CRegister cr) {
-  if (::v8::internal::FLAG_trace_sim_stubs) {
-    emit(0x7d9ff808);
-#if V8_TARGET_ARCH_PPC64
-    uint64_t value = reinterpret_cast<uint64_t>(msg);
-    emit(static_cast<uint32_t>(value >> 32));
-    emit(static_cast<uint32_t>(value & 0xFFFFFFFF));
-#else
-    emit(reinterpret_cast<Instr>(msg));
-#endif
-  }
-}
-
-
 void Assembler::dcbf(Register ra, Register rb) {
   emit(EXT2 | DCBF | ra.code() * B16 | rb.code() * B11);
 }
 
 
 void Assembler::sync() { emit(EXT2 | SYNC); }
 
 
 void Assembler::lwsync() { emit(EXT2 | SYNC | 1 * B21); }
 
@@ skipping 207 matching lines @@
 void Assembler::fctiwz(const DoubleRegister frt, const DoubleRegister frb) {
   emit(EXT4 | FCTIWZ | frt.code() * B21 | frb.code() * B11);
 }
 
 
 void Assembler::fctiw(const DoubleRegister frt, const DoubleRegister frb) {
   emit(EXT4 | FCTIW | frt.code() * B21 | frb.code() * B11);
 }
 
 
-void Assembler::frim(const DoubleRegister frt, const DoubleRegister frb) {
-  emit(EXT4 | FRIM | frt.code() * B21 | frb.code() * B11);
+void Assembler::frin(const DoubleRegister frt, const DoubleRegister frb,
+                     RCBit rc) {
+  emit(EXT4 | FRIN | frt.code() * B21 | frb.code() * B11 | rc);
 }
 
 
+void Assembler::friz(const DoubleRegister frt, const DoubleRegister frb,
+                     RCBit rc) {
+  emit(EXT4 | FRIZ | frt.code() * B21 | frb.code() * B11 | rc);
+}
+
+
+void Assembler::frip(const DoubleRegister frt, const DoubleRegister frb,
+                     RCBit rc) {
+  emit(EXT4 | FRIP | frt.code() * B21 | frb.code() * B11 | rc);
+}
+
+
+void Assembler::frim(const DoubleRegister frt, const DoubleRegister frb,
+                     RCBit rc) {
+  emit(EXT4 | FRIM | frt.code() * B21 | frb.code() * B11 | rc);
+}
+
+
 void Assembler::frsp(const DoubleRegister frt, const DoubleRegister frb,
                      RCBit rc) {
   emit(EXT4 | FRSP | frt.code() * B21 | frb.code() * B11 | rc);
 }
 
 
 void Assembler::fcfid(const DoubleRegister frt, const DoubleRegister frb,
                       RCBit rc) {
   emit(EXT4 | FCFID | frt.code() * B21 | frb.code() * B11 | rc);
 }
@@ skipping 125 matching lines @@
 
 
 void Assembler::RecordComment(const char* msg) {
   if (FLAG_code_comments) {
     CheckBuffer();
     RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
   }
 }
 
 
+void Assembler::RecordDeoptReason(const int reason, const int raw_position) {
+  if (FLAG_trace_deopt) {
+    EnsureSpace ensure_space(this);
+    RecordRelocInfo(RelocInfo::POSITION, raw_position);
+    RecordRelocInfo(RelocInfo::DEOPT_REASON, reason);
+  }
+}
+
+
 void Assembler::GrowBuffer() {
   if (!own_buffer_) FATAL("external code buffer is too small");
 
   // Compute new buffer size.
   CodeDesc desc;  // the new buffer
   if (buffer_size_ < 4 * KB) {
     desc.buffer_size = 4 * KB;
   } else if (buffer_size_ < 1 * MB) {
     desc.buffer_size = 2 * buffer_size_;
   } else {
@@ skipping 337 matching lines @@
 
     // Patch load instruction with correct offset.
     Assembler::SetConstantPoolOffset(rinfo.pc(), offset);
   }
 }
 #endif
 }
 }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_PPC