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| 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. |
| 4 |
| 5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
| 6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
| 7 |
| 8 namespace v8 { |
| 9 namespace internal { |
| 10 namespace compiler { |
| 11 |
| 12 // PPC-specific opcodes that specify which assembly sequence to emit. |
| 13 // Most opcodes specify a single instruction. |
| 14 #define TARGET_ARCH_OPCODE_LIST(V) \ |
| 15 V(PPC_And32) \ |
| 16 V(PPC_And64) \ |
| 17 V(PPC_AndComplement32) \ |
| 18 V(PPC_AndComplement64) \ |
| 19 V(PPC_Or32) \ |
| 20 V(PPC_Or64) \ |
| 21 V(PPC_OrComplement32) \ |
| 22 V(PPC_OrComplement64) \ |
| 23 V(PPC_Xor32) \ |
| 24 V(PPC_Xor64) \ |
| 25 V(PPC_ShiftLeft32) \ |
| 26 V(PPC_ShiftLeft64) \ |
| 27 V(PPC_ShiftRight32) \ |
| 28 V(PPC_ShiftRight64) \ |
| 29 V(PPC_ShiftRightAlg32) \ |
| 30 V(PPC_ShiftRightAlg64) \ |
| 31 V(PPC_RotRight32) \ |
| 32 V(PPC_RotRight64) \ |
| 33 V(PPC_Not32) \ |
| 34 V(PPC_Not64) \ |
| 35 V(PPC_RotLeftAndMask32) \ |
| 36 V(PPC_RotLeftAndClear64) \ |
| 37 V(PPC_RotLeftAndClearLeft64) \ |
| 38 V(PPC_RotLeftAndClearRight64) \ |
| 39 V(PPC_Add32) \ |
| 40 V(PPC_AddWithOverflow32) \ |
| 41 V(PPC_Add64) \ |
| 42 V(PPC_AddFloat64) \ |
| 43 V(PPC_Sub32) \ |
| 44 V(PPC_SubWithOverflow32) \ |
| 45 V(PPC_Sub64) \ |
| 46 V(PPC_SubFloat64) \ |
| 47 V(PPC_Mul32) \ |
| 48 V(PPC_Mul64) \ |
| 49 V(PPC_MulHigh32) \ |
| 50 V(PPC_MulHighU32) \ |
| 51 V(PPC_MulFloat64) \ |
| 52 V(PPC_Div32) \ |
| 53 V(PPC_Div64) \ |
| 54 V(PPC_DivU32) \ |
| 55 V(PPC_DivU64) \ |
| 56 V(PPC_DivFloat64) \ |
| 57 V(PPC_Mod32) \ |
| 58 V(PPC_Mod64) \ |
| 59 V(PPC_ModU32) \ |
| 60 V(PPC_ModU64) \ |
| 61 V(PPC_ModFloat64) \ |
| 62 V(PPC_Neg32) \ |
| 63 V(PPC_Neg64) \ |
| 64 V(PPC_NegFloat64) \ |
| 65 V(PPC_SqrtFloat64) \ |
| 66 V(PPC_FloorFloat64) \ |
| 67 V(PPC_CeilFloat64) \ |
| 68 V(PPC_TruncateFloat64) \ |
| 69 V(PPC_RoundFloat64) \ |
| 70 V(PPC_Cmp32) \ |
| 71 V(PPC_Cmp64) \ |
| 72 V(PPC_CmpFloat64) \ |
| 73 V(PPC_Tst32) \ |
| 74 V(PPC_Tst64) \ |
| 75 V(PPC_Push) \ |
| 76 V(PPC_ExtendSignWord8) \ |
| 77 V(PPC_ExtendSignWord16) \ |
| 78 V(PPC_ExtendSignWord32) \ |
| 79 V(PPC_Uint32ToUint64) \ |
| 80 V(PPC_Int64ToInt32) \ |
| 81 V(PPC_Int32ToFloat64) \ |
| 82 V(PPC_Uint32ToFloat64) \ |
| 83 V(PPC_Float32ToFloat64) \ |
| 84 V(PPC_Float64ToInt32) \ |
| 85 V(PPC_Float64ToUint32) \ |
| 86 V(PPC_Float64ToFloat32) \ |
| 87 V(PPC_LoadWordS8) \ |
| 88 V(PPC_LoadWordU8) \ |
| 89 V(PPC_LoadWordS16) \ |
| 90 V(PPC_LoadWordU16) \ |
| 91 V(PPC_LoadWordS32) \ |
| 92 V(PPC_LoadWord64) \ |
| 93 V(PPC_LoadFloat32) \ |
| 94 V(PPC_LoadFloat64) \ |
| 95 V(PPC_StoreWord8) \ |
| 96 V(PPC_StoreWord16) \ |
| 97 V(PPC_StoreWord32) \ |
| 98 V(PPC_StoreWord64) \ |
| 99 V(PPC_StoreFloat32) \ |
| 100 V(PPC_StoreFloat64) \ |
| 101 V(PPC_StoreWriteBarrier) |
| 102 |
| 103 |
| 104 // Addressing modes represent the "shape" of inputs to an instruction. |
| 105 // Many instructions support multiple addressing modes. Addressing modes |
| 106 // are encoded into the InstructionCode of the instruction and tell the |
| 107 // code generator after register allocation which assembler method to call. |
| 108 // |
| 109 // We use the following local notation for addressing modes: |
| 110 // |
| 111 // R = register |
| 112 // O = register or stack slot |
| 113 // D = double register |
| 114 // I = immediate (handle, external, int32) |
| 115 // MRI = [register + immediate] |
| 116 // MRR = [register + register] |
| 117 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 118 V(MRI) /* [%r0 + K] */ \ |
| 119 V(MRR) /* [%r0 + %r1] */ |
| 120 |
| 121 } // namespace compiler |
| 122 } // namespace internal |
| 123 } // namespace v8 |
| 124 |
| 125 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
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