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1 // Copyright 2014 The Crashpad Authors. All rights reserved. | 1 // Copyright 2014 The Crashpad Authors. All rights reserved. |
2 // | 2 // |
3 // Licensed under the Apache License, Version 2.0 (the "License"); | 3 // Licensed under the Apache License, Version 2.0 (the "License"); |
4 // you may not use this file except in compliance with the License. | 4 // you may not use this file except in compliance with the License. |
5 // You may obtain a copy of the License at | 5 // You may obtain a copy of the License at |
6 // | 6 // |
7 // http://www.apache.org/licenses/LICENSE-2.0 | 7 // http://www.apache.org/licenses/LICENSE-2.0 |
8 // | 8 // |
9 // Unless required by applicable law or agreed to in writing, software | 9 // Unless required by applicable law or agreed to in writing, software |
10 // distributed under the License is distributed on an "AS IS" BASIS, | 10 // distributed under the License is distributed on an "AS IS" BASIS, |
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112 context->r8 = value++; | 112 context->r8 = value++; |
113 context->r9 = value++; | 113 context->r9 = value++; |
114 context->r10 = value++; | 114 context->r10 = value++; |
115 context->r11 = value++; | 115 context->r11 = value++; |
116 context->r12 = value++; | 116 context->r12 = value++; |
117 context->r13 = value++; | 117 context->r13 = value++; |
118 context->r14 = value++; | 118 context->r14 = value++; |
119 context->r15 = value++; | 119 context->r15 = value++; |
120 context->rip = value++; | 120 context->rip = value++; |
121 context->eflags = value++; | 121 context->eflags = value++; |
122 context->cs = value++; | 122 context->cs = static_cast<uint16_t>(value++); |
123 context->fs = value++; | 123 context->fs = static_cast<uint16_t>(value++); |
124 context->gs = value++; | 124 context->gs = static_cast<uint16_t>(value++); |
125 | 125 |
126 InitializeCPUContextX86_64Fxsave(&context->fxsave, &value); | 126 InitializeCPUContextX86_64Fxsave(&context->fxsave, &value); |
127 | 127 |
128 // mxcsr appears twice, and the two values should be aliased. | 128 // mxcsr appears twice, and the two values should be aliased. |
129 context->mx_csr = context->fxsave.mxcsr; | 129 context->mx_csr = context->fxsave.mxcsr; |
130 | 130 |
131 context->dr0 = value++; | 131 context->dr0 = value++; |
132 context->dr1 = value++; | 132 context->dr1 = value++; |
133 context->dr2 = value++; | 133 context->dr2 = value++; |
134 context->dr3 = value++; | 134 context->dr3 = value++; |
135 value += 2; // Minidumps don’t carry dr4 or dr5. | 135 value += 2; // Minidumps don’t carry dr4 or dr5. |
136 context->dr6 = value++; | 136 context->dr6 = value++; |
137 context->dr7 = value++; | 137 context->dr7 = value++; |
138 | 138 |
139 // Set these fields last, because they have no analogues in CPUContextX86_64. | 139 // Set these fields last, because they have no analogues in CPUContextX86_64. |
140 context->p1_home = value++; | 140 context->p1_home = value++; |
141 context->p2_home = value++; | 141 context->p2_home = value++; |
142 context->p3_home = value++; | 142 context->p3_home = value++; |
143 context->p4_home = value++; | 143 context->p4_home = value++; |
144 context->p5_home = value++; | 144 context->p5_home = value++; |
145 context->p6_home = value++; | 145 context->p6_home = value++; |
146 context->ds = value++; | 146 context->ds = static_cast<uint16_t>(value++); |
147 context->es = value++; | 147 context->es = static_cast<uint16_t>(value++); |
148 context->ss = value++; | 148 context->ss = static_cast<uint16_t>(value++); |
149 for (size_t index = 0; index < arraysize(context->vector_register); ++index) { | 149 for (size_t index = 0; index < arraysize(context->vector_register); ++index) { |
150 context->vector_register[index].lo = value++; | 150 context->vector_register[index].lo = value++; |
151 context->vector_register[index].hi = value++; | 151 context->vector_register[index].hi = value++; |
152 } | 152 } |
153 context->vector_control = value++; | 153 context->vector_control = value++; |
154 context->debug_control = value++; | 154 context->debug_control = value++; |
155 context->last_branch_to_rip = value++; | 155 context->last_branch_to_rip = value++; |
156 context->last_branch_from_rip = value++; | 156 context->last_branch_from_rip = value++; |
157 context->last_exception_to_rip = value++; | 157 context->last_exception_to_rip = value++; |
158 context->last_exception_from_rip = value++; | 158 context->last_exception_from_rip = value++; |
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370 EXPECT_EQ(expected.last_branch_to_rip, observed->last_branch_to_rip); | 370 EXPECT_EQ(expected.last_branch_to_rip, observed->last_branch_to_rip); |
371 EXPECT_EQ(expected.last_branch_from_rip, observed->last_branch_from_rip); | 371 EXPECT_EQ(expected.last_branch_from_rip, observed->last_branch_from_rip); |
372 EXPECT_EQ(expected.last_exception_to_rip, observed->last_exception_to_rip); | 372 EXPECT_EQ(expected.last_exception_to_rip, observed->last_exception_to_rip); |
373 EXPECT_EQ(expected.last_exception_from_rip, | 373 EXPECT_EQ(expected.last_exception_from_rip, |
374 observed->last_exception_from_rip); | 374 observed->last_exception_from_rip); |
375 } | 375 } |
376 } | 376 } |
377 | 377 |
378 } // namespace test | 378 } // namespace test |
379 } // namespace crashpad | 379 } // namespace crashpad |
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