MIPS: [turbofan] Initial support for Switch.

src/compiler/mips/code-generator-mips.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
 #include "src/compiler/node-matchers.h"
 #include "src/mips/macro-assembler-mips.h"
 #include "src/scopes.h"
@@ skipping 410 matching lines @@
       }
 
       __ lw(at, FieldMemOperand(func, JSFunction::kCodeEntryOffset));
       __ Call(at);
       AddSafepointAndDeopt(instr);
       break;
     }
     case kArchJmp:
       AssembleArchJump(i.InputRpo(0));
       break;
+    case kArchSwitch:
+      AssembleArchSwitch(instr);
+      break;
     case kArchNop:
       // don't emit code for nops.
       break;
     case kArchRet:
       AssembleReturn();
       break;
     case kArchStackPointer:
       __ mov(i.OutputRegister(), sp);
       break;
     case kArchTruncateDoubleToI:
@@ skipping 354 matching lines @@
     UNIMPLEMENTED();
   }
 }
 
 
 void CodeGenerator::AssembleArchJump(BasicBlock::RpoNumber target) {
   if (!IsNextInAssemblyOrder(target)) __ Branch(GetLabel(target));
 }
 
 
+void CodeGenerator::AssembleArchSwitch(Instruction* instr) {
+  MipsOperandConverter i(this, instr);
+  int const kNumLabels = static_cast<int>(instr->InputCount() - 1);
+  v8::internal::Assembler::BlockTrampolinePoolScope block_trampoline_pool(
+      masm());
+  Label here;
+
+  __ bal(&here);
+  __ nop();  // Branch delay slot nop.
+  __ bind(&here);
+  __ sll(at, i.InputRegister(0), 2);
+  __ addu(at, at, ra);
+  __ lw(at, MemOperand(at, 5 * v8::internal::Assembler::kInstrSize));
+  __ jr(at);
+  __ nop();  // Branch delay slot nop.
+
+  for (int index = 0; index < kNumLabels; ++index) {
+    __ dd(GetLabel(i.InputRpo(index + 1)));
+  }
+}
+
+
 // Assembles boolean materializations after an instruction.
 void CodeGenerator::AssembleArchBoolean(Instruction* instr,
                                         FlagsCondition condition) {
   MipsOperandConverter i(this, instr);
   Label done;
 
   // Materialize a full 32-bit 1 or 0 value. The result register is always the
   // last output of the instruction.
   Label false_value;
   DCHECK_NE(0u, instr->OutputCount());
@@ skipping 304 matching lines @@
     __ lw(temp_0, src1);
     __ sw(temp_0, dst1);
     __ sdc1(temp_1, src0);
   } else {
     // No other combinations are possible.
     UNREACHABLE();
   }
 }
 
 
+void CodeGenerator::AssembleJumpTable(Label** targets, size_t target_count) {
+  // On 32-bit MIPS we emit the jump tables inline.
+  UNREACHABLE();
+}
+
+
 void CodeGenerator::AddNopForSmiCodeInlining() {
   // Unused on 32-bit ARM. Still exists on 64-bit arm.
   // TODO(plind): Unclear when this is called now. Understand, fix if needed.
   __ nop();  // Maybe PROPERTY_ACCESS_INLINED?
 }
 
 
 void CodeGenerator::EnsureSpaceForLazyDeopt() {
   int space_needed = Deoptimizer::patch_size();
   if (!info()->IsStub()) {
@@ skipping 13 matching lines @@
     }
   }
   MarkLazyDeoptSite();
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8