Add OrderingBarrierCHROMIUM API.

content/common/gpu/client/gpu_channel_host.cc

Index: content/common/gpu/client/gpu_channel_host.cc
diff --git a/content/common/gpu/client/gpu_channel_host.cc b/content/common/gpu/client/gpu_channel_host.cc
index be28c50c73e3ac2de6b926a4195b1f0c0ebc5715..b58f9df5b83e7717cfcfeb3e54e5685bf9c0be69 100644
--- a/content/common/gpu/client/gpu_channel_host.cc
+++ b/content/common/gpu/client/gpu_channel_host.cc
@@ -30,6 +30,13 @@ GpuListenerInfo::GpuListenerInfo() {}
 
 GpuListenerInfo::~GpuListenerInfo() {}
 
+ProxyFlushInfo::ProxyFlushInfo()
+    : flush_pending(false), route_id(0), put_offset(0), flush_count(0) {
+}
+
+ProxyFlushInfo::~ProxyFlushInfo() {
+}
+
 // static
 scoped_refptr<GpuChannelHost> GpuChannelHost::Create(
     GpuChannelHostFactory* factory,
@@ -80,6 +87,12 @@ void GpuChannelHost::Connect(const IPC::ChannelHandle& channel_handle,
 }
 
 bool GpuChannelHost::Send(IPC::Message* msg) {
+  AutoLock lock(context_lock_);
+  InternalFlush();
+  return InternalSend(msg);

[piman, 2015/02/05 01:14:15]

The main thing is that some of the messages are synchronous, and keeping the
lock while sending those is unfortunate (e.g. if it's a
WaitForGetOffsetInRange/WaitForTokenInRange which can be arbitrary long).

I /think/ it's ok to release after the InternalFlush, but it's subtle. The
argument is that if there's 2 (or more) threads trying to send a message "at the
same time" (without mutual exclusion), then they don't have an ordering
dependency between them (because nothing currently would guarantee ordering).
The only potential dependencies are between any previous Flush and each of the
message. The first one of these messages gets to grab the lock, and ensures that
the Flush will happen before that message, but also before any other message
will go through.

[vmiura, 2015/02/05 01:20:48]

Makes sense.

I think doing InternalFlush on every Send may be overkill.  Certain IPCs must be
ordered relative to the pending Flush(), but I'm not sure which.

For one, would it be sufficient to run InternalFlush() when the Send is from the
same route_id as the pending Flush?

Then, are there only specific IPCs within the route that need strict ordering
with the Flush?

+}
+
+bool GpuChannelHost::InternalSend(IPC::Message* msg) {
   // Callee takes ownership of message, regardless of whether Send is
   // successful. See IPC::Sender.
   scoped_ptr<IPC::Message> message(msg);
@@ -112,6 +125,36 @@ bool GpuChannelHost::Send(IPC::Message* msg) {
   return false;
 }
 
+void GpuChannelHost::Flush(int route_id,
+                           int32 put_offset,
+                           uint32 flush_count,
+                           const std::vector<ui::LatencyInfo>& latency_info,
+                           bool shallow_flush) {
+  AutoLock lock(context_lock_);
+  if (flush_info_.flush_pending && flush_info_.route_id != route_id)
+    InternalFlush();
+
+  flush_info_.flush_pending = true;
+  flush_info_.route_id = route_id;
+  flush_info_.put_offset = put_offset;
+  flush_info_.flush_count = flush_count;
+  flush_info_.latency_info.insert(flush_info_.latency_info.end(),
+                                  latency_info.begin(), latency_info.end());
+
+  if (!shallow_flush)
+    InternalFlush();
+}
+
+void GpuChannelHost::InternalFlush() {
+  if (flush_info_.flush_pending) {
+    InternalSend(new GpuCommandBufferMsg_AsyncFlush(
+        flush_info_.route_id, flush_info_.put_offset, flush_info_.flush_count,
+        flush_info_.latency_info));
+    flush_info_.latency_info.clear();
+    flush_info_.flush_pending = false;
+  }
+}
+
 CommandBufferProxyImpl* GpuChannelHost::CreateViewCommandBuffer(
     int32 surface_id,
     CommandBufferProxyImpl* share_group,
@@ -229,6 +272,9 @@ void GpuChannelHost::DestroyCommandBuffer(
 
   AutoLock lock(context_lock_);
   proxies_.erase(route_id);
+  if (flush_info_.flush_pending && flush_info_.route_id == route_id)
+    flush_info_.flush_pending = false;
+
   delete command_buffer;
 }