Revert "Make GCC happy again." and "Initial switch to Chromium-style CHECK_* and DCHECK_* macros.".

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
 namespace v8 {
@@ skipping 215 matching lines @@
   if (cont->IsBranch()) {
     inputs[input_count++] = g.Label(cont->true_block());
     inputs[input_count++] = g.Label(cont->false_block());
   }
 
   outputs[output_count++] = g.DefineAsRegister(node);
   if (cont->IsSet()) {
     outputs[output_count++] = g.DefineAsRegister(cont->result());
   }
 
-  DCHECK_NE(0u, input_count);
-  DCHECK_NE(0u, output_count);
+  DCHECK_NE(0, input_count);
+  DCHECK_NE(0, output_count);
   DCHECK_GE(arraysize(inputs), input_count);
   DCHECK_GE(arraysize(outputs), output_count);
   DCHECK_NE(kMode_None, AddressingModeField::decode(opcode));
 
   Instruction* instr = selector->Emit(cont->Encode(opcode), output_count,
                                       outputs, input_count, inputs);
   if (cont->IsBranch()) instr->MarkAsControl();
 }
 
 
@@ skipping 193 matching lines @@
     return;
   }
   selector->Emit(opcode | AddressingModeField::encode(kMode_Operand2_R),
                  g.DefineAsRegister(node), g.UseRegister(left),
                  g.UseRegister(right));
 }
 
 
 void EmitUbfx(InstructionSelector* selector, Node* node, Node* left,
               uint32_t lsb, uint32_t width) {
-  DCHECK_LE(1u, width);
-  DCHECK_LE(width, 32u - lsb);
+  DCHECK_LE(1, width);
+  DCHECK_LE(width, 32 - lsb);
   ArmOperandGenerator g(selector);
   selector->Emit(kArmUbfx, g.DefineAsRegister(node), g.UseRegister(left),
                  g.TempImmediate(lsb), g.TempImmediate(width));
 }
 
 }  // namespace
 
 
 void InstructionSelector::VisitWord32And(Node* node) {
   ArmOperandGenerator g(this);
@@ skipping 11 matching lines @@
       EmitBic(this, node, m.left().node(), mright.left().node());
       return;
     }
   }
   if (m.right().HasValue()) {
     uint32_t const value = m.right().Value();
     uint32_t width = base::bits::CountPopulation32(value);
     uint32_t msb = base::bits::CountLeadingZeros32(value);
     // Try to interpret this AND as UBFX.
     if (IsSupported(ARMv7) && width != 0 && msb + width == 32) {
-      DCHECK_EQ(0u, base::bits::CountTrailingZeros32(value));
+      DCHECK_EQ(0, base::bits::CountTrailingZeros32(value));
       if (m.left().IsWord32Shr()) {
         Int32BinopMatcher mleft(m.left().node());
         if (mleft.right().IsInRange(0, 31)) {
           // UBFX cannot extract bits past the register size, however since
           // shifting the original value would have introduced some zeros we can
           // still use UBFX with a smaller mask and the remaining bits will be
           // zeros.
           uint32_t const lsb = mleft.right().Value();
           return EmitUbfx(this, node, mleft.left().node(), lsb,
                           std::min(width, 32 - lsb));
@@ skipping 48 matching lines @@
       return;
     }
     Emit(opcode | AddressingModeField::encode(kMode_Operand2_R),
          g.DefineAsRegister(node), g.UseRegister(m.left().node()));
     return;
   }
   VisitBinop(this, node, kArmEor, kArmEor);
 }
 
 
-namespace {
-
 template <typename TryMatchShift>
-void VisitShift(InstructionSelector* selector, Node* node,
-                TryMatchShift try_match_shift, FlagsContinuation* cont) {
+static inline void VisitShift(InstructionSelector* selector, Node* node,
+                              TryMatchShift try_match_shift,
+                              FlagsContinuation* cont) {
   ArmOperandGenerator g(selector);
   InstructionCode opcode = kArmMov;
   InstructionOperand* inputs[4];
   size_t input_count = 2;
   InstructionOperand* outputs[2];
   size_t output_count = 0;
 
   CHECK(try_match_shift(selector, &opcode, node, &inputs[0], &inputs[1]));
 
   if (cont->IsBranch()) {
     inputs[input_count++] = g.Label(cont->true_block());
     inputs[input_count++] = g.Label(cont->false_block());
   }
 
   outputs[output_count++] = g.DefineAsRegister(node);
   if (cont->IsSet()) {
     outputs[output_count++] = g.DefineAsRegister(cont->result());
   }
 
-  DCHECK_NE(0u, input_count);
-  DCHECK_NE(0u, output_count);
+  DCHECK_NE(0, input_count);
+  DCHECK_NE(0, output_count);
   DCHECK_GE(arraysize(inputs), input_count);
   DCHECK_GE(arraysize(outputs), output_count);
   DCHECK_NE(kMode_None, AddressingModeField::decode(opcode));
 
   Instruction* instr = selector->Emit(cont->Encode(opcode), output_count,
                                       outputs, input_count, inputs);
   if (cont->IsBranch()) instr->MarkAsControl();
 }
 
 
 template <typename TryMatchShift>
-void VisitShift(InstructionSelector* selector, Node* node,
+static inline void VisitShift(InstructionSelector* selector, Node* node,
                               TryMatchShift try_match_shift) {
   FlagsContinuation cont;
   VisitShift(selector, node, try_match_shift, &cont);
 }
 
-}  // namespace
-
 
 void InstructionSelector::VisitWord32Shl(Node* node) {
   VisitShift(this, node, TryMatchLSL);
 }
 
 
 void InstructionSelector::VisitWord32Shr(Node* node) {
   ArmOperandGenerator g(this);
   Int32BinopMatcher m(node);
   if (IsSupported(ARMv7) && m.left().IsWord32And() &&
       m.right().IsInRange(0, 31)) {
-    uint32_t lsb = m.right().Value();
+    int32_t lsb = m.right().Value();
     Int32BinopMatcher mleft(m.left().node());
     if (mleft.right().HasValue()) {
       uint32_t value = (mleft.right().Value() >> lsb) << lsb;
       uint32_t width = base::bits::CountPopulation32(value);
       uint32_t msb = base::bits::CountLeadingZeros32(value);
       if (msb + width + lsb == 32) {
         DCHECK_EQ(lsb, base::bits::CountTrailingZeros32(value));
         return EmitUbfx(this, node, mleft.left().node(), lsb, width);
       }
     }
@@ skipping 499 matching lines @@
   }
 
   if (cont->IsBranch()) {
     inputs[input_count++] = g.Label(cont->true_block());
     inputs[input_count++] = g.Label(cont->false_block());
   } else {
     DCHECK(cont->IsSet());
     outputs[output_count++] = g.DefineAsRegister(cont->result());
   }
 
-  DCHECK_NE(0u, input_count);
+  DCHECK_NE(0, input_count);
   DCHECK_GE(arraysize(inputs), input_count);
   DCHECK_GE(arraysize(outputs), output_count);
 
   Instruction* instr = selector->Emit(cont->Encode(opcode), output_count,
                                       outputs, input_count, inputs);
   if (cont->IsBranch()) instr->MarkAsControl();
 }
 
 
 void VisitWordCompare(InstructionSelector* selector, Node* node,
@@ skipping 199 matching lines @@
              MachineOperatorBuilder::kFloat64Ceil |
              MachineOperatorBuilder::kFloat64RoundTruncate |
              MachineOperatorBuilder::kFloat64RoundTiesAway;
   }
   return flags;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8