[turbofan] Initial support for Switch.

src/compiler/instruction-selector.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/instruction-selector.h"
 
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 #include "src/compiler/pipeline.h"
@@ skipping 465 matching lines @@
   // We're done with the block.
   InstructionBlock* instruction_block =
       sequence()->InstructionBlockAt(block->GetRpoNumber());
   instruction_block->set_code_start(static_cast<int>(instructions_.size()));
   instruction_block->set_code_end(current_block_end);
 
   current_block_ = NULL;
 }
 
 
-static inline void CheckNoPhis(const BasicBlock* block) {
+namespace {
+
+V8_INLINE void CheckNoPhis(const BasicBlock* block) {
 #ifdef DEBUG
   // Branch targets should not have phis.
   for (BasicBlock::const_iterator i = block->begin(); i != block->end(); ++i) {
     const Node* node = *i;
     CHECK_NE(IrOpcode::kPhi, node->opcode());
   }
 #endif
 }
 
+}  // namespace
+
 
 void InstructionSelector::VisitControl(BasicBlock* block) {
   Node* input = block->control_input();
   switch (block->control()) {
     case BasicBlock::kGoto:
       return VisitGoto(block->SuccessorAt(0));
     case BasicBlock::kBranch: {
       DCHECK_EQ(IrOpcode::kBranch, input->opcode());
       BasicBlock* tbranch = block->SuccessorAt(0);
       BasicBlock* fbranch = block->SuccessorAt(1);
       // SSA deconstruction requires targets of branches not to have phis.
       // Edge split form guarantees this property, but is more strict.
       CheckNoPhis(tbranch);
       CheckNoPhis(fbranch);
       if (tbranch == fbranch) return VisitGoto(tbranch);
       // Treat special Branch(Always, IfTrue, IfFalse) as Goto(IfTrue).
       Node* const condition = input->InputAt(0);
       if (condition->opcode() == IrOpcode::kAlways) return VisitGoto(tbranch);
       return VisitBranch(input, tbranch, fbranch);
     }
+    case BasicBlock::kSwitch: {
+      DCHECK_EQ(IrOpcode::kSwitch, input->opcode());
+      BasicBlock** const branches = &block->successors().front();
+      size_t const branch_count = block->SuccessorCount();
+      DCHECK_LE(2u, branch_count);
+      // SSA deconstruction requires targets of branches not to have phis.
+      // Edge split form guarantees this property, but is more strict.
+      for (size_t index = 0; index < branch_count; ++index) {
+        CheckNoPhis(branches[index]);
+      }
+      return VisitSwitch(input, branches, branch_count);
+    }
     case BasicBlock::kReturn: {
       // If the result itself is a return, return its input.
       Node* value = (input != NULL && input->opcode() == IrOpcode::kReturn)
                         ? input->InputAt(0)
                         : input;
       return VisitReturn(value);
     }
     case BasicBlock::kThrow:
       DCHECK_EQ(IrOpcode::kThrow, input->opcode());
       return VisitThrow(input->InputAt(0));
     case BasicBlock::kNone: {
       // TODO(titzer): exit block doesn't have control.
-      DCHECK(input == NULL);
+      DCHECK_NULL(input);
       break;
     }
     default:
       UNREACHABLE();
       break;
   }
 }
 
 
 MachineType InstructionSelector::GetMachineType(Node* node) {
   DCHECK_NOT_NULL(schedule()->block(node));  // should only use scheduled nodes.
   switch (node->opcode()) {
     case IrOpcode::kStart:
     case IrOpcode::kLoop:
     case IrOpcode::kEnd:
     case IrOpcode::kBranch:
     case IrOpcode::kIfTrue:
     case IrOpcode::kIfFalse:
+    case IrOpcode::kSwitch:
+    case IrOpcode::kCase:
     case IrOpcode::kEffectPhi:
     case IrOpcode::kEffectSet:
     case IrOpcode::kMerge:
       // No code needed for these graph artifacts.
       return kMachNone;
     case IrOpcode::kFinish:
       return kMachAnyTagged;
     case IrOpcode::kParameter:
       return linkage()->GetParameterType(OpParameter<int>(node));
     case IrOpcode::kOsrValue:
@@ skipping 118 matching lines @@
       Emit(SourcePositionInstruction::New(instruction_zone(), source_position));
     }
   }
   switch (node->opcode()) {
     case IrOpcode::kStart:
     case IrOpcode::kLoop:
     case IrOpcode::kEnd:
     case IrOpcode::kBranch:
     case IrOpcode::kIfTrue:
     case IrOpcode::kIfFalse:
+    case IrOpcode::kSwitch:
+    case IrOpcode::kCase:
     case IrOpcode::kEffectPhi:
     case IrOpcode::kMerge:
       // No code needed for these graph artifacts.
       return;
     case IrOpcode::kFinish:
       return MarkAsReference(node), VisitFinish(node);
     case IrOpcode::kParameter: {
       MachineType type = linkage()->GetParameterType(OpParameter<int>(node));
       MarkAsRepresentation(type, node);
       return VisitParameter(node);
@@ skipping 336 matching lines @@
 }
 
 
 void InstructionSelector::VisitGoto(BasicBlock* target) {
   // jump to the next block.
   OperandGenerator g(this);
   Emit(kArchJmp, g.NoOutput(), g.Label(target))->MarkAsControl();
 }
 
 
+void InstructionSelector::VisitSwitch(Node* node, BasicBlock** branches,
+                                      size_t branch_count) {
+  OperandGenerator g(this);
+  Node* const value = node->InputAt(0);
+  size_t const input_count = branch_count + 1;
+  InstructionOperand* const inputs =
+      zone()->NewArray<InstructionOperand>(static_cast<int>(input_count));
+  inputs[0] = g.UseRegister(value);
+  for (size_t index = 0; index < branch_count; ++index) {
+    inputs[index + 1] = g.Label(branches[index]);
+  }
+  Emit(kArchSwitch, 0, nullptr, input_count, inputs, 0, nullptr)
+      ->MarkAsControl();
+}
+
+
 void InstructionSelector::VisitReturn(Node* value) {
   OperandGenerator g(this);
   if (value != NULL) {
     Emit(kArchRet, g.NoOutput(),
          g.UseLocation(value, linkage()->GetReturnLocation(),
                        linkage()->GetReturnType()));
   } else {
     Emit(kArchRet, g.NoOutput());
   }
 }
@@ skipping 125 matching lines @@
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   return MachineOperatorBuilder::Flag::kNoFlags;
 }
 
 #endif  // !V8_TURBOFAN_BACKEND
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8