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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/base/utils/random-number-generator.h" | 5 #include "src/base/utils/random-number-generator.h" |
6 #include "src/compiler/pipeline.h" | 6 #include "src/compiler/pipeline.h" |
7 #include "test/unittests/compiler/instruction-sequence-unittest.h" | 7 #include "test/unittests/compiler/instruction-sequence-unittest.h" |
8 #include "test/unittests/test-utils.h" | 8 #include "test/unittests/test-utils.h" |
9 #include "testing/gmock/include/gmock/gmock.h" | 9 #include "testing/gmock/include/gmock/gmock.h" |
10 | 10 |
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131 | 131 |
132 InstructionSequenceTest::TestOperand InstructionSequenceTest::Imm(int32_t imm) { | 132 InstructionSequenceTest::TestOperand InstructionSequenceTest::Imm(int32_t imm) { |
133 int index = sequence()->AddImmediate(Constant(imm)); | 133 int index = sequence()->AddImmediate(Constant(imm)); |
134 return TestOperand(kImmediate, index); | 134 return TestOperand(kImmediate, index); |
135 } | 135 } |
136 | 136 |
137 | 137 |
138 InstructionSequenceTest::VReg InstructionSequenceTest::Define( | 138 InstructionSequenceTest::VReg InstructionSequenceTest::Define( |
139 TestOperand output_op) { | 139 TestOperand output_op) { |
140 VReg vreg = NewReg(); | 140 VReg vreg = NewReg(); |
141 InstructionOperand* outputs[1]{ConvertOutputOp(vreg, output_op)}; | 141 InstructionOperand outputs[1]{ConvertOutputOp(vreg, output_op)}; |
142 Emit(vreg.value_, kArchNop, 1, outputs); | 142 Emit(vreg.value_, kArchNop, 1, outputs); |
143 return vreg; | 143 return vreg; |
144 } | 144 } |
145 | 145 |
146 | 146 |
147 int InstructionSequenceTest::Return(TestOperand input_op_0) { | 147 int InstructionSequenceTest::Return(TestOperand input_op_0) { |
148 block_returns_ = true; | 148 block_returns_ = true; |
149 InstructionOperand* inputs[1]{ConvertInputOp(input_op_0)}; | 149 InstructionOperand inputs[1]{ConvertInputOp(input_op_0)}; |
150 return Emit(NewIndex(), kArchRet, 0, nullptr, 1, inputs); | 150 return Emit(NewIndex(), kArchRet, 0, nullptr, 1, inputs); |
151 } | 151 } |
152 | 152 |
153 | 153 |
154 PhiInstruction* InstructionSequenceTest::Phi(VReg incoming_vreg_0, | 154 PhiInstruction* InstructionSequenceTest::Phi(VReg incoming_vreg_0, |
155 VReg incoming_vreg_1, | 155 VReg incoming_vreg_1, |
156 VReg incoming_vreg_2, | 156 VReg incoming_vreg_2, |
157 VReg incoming_vreg_3) { | 157 VReg incoming_vreg_3) { |
158 auto phi = new (zone()) PhiInstruction(zone(), NewReg().value_, 10); | 158 auto phi = new (zone()) PhiInstruction(zone(), NewReg().value_, 10); |
159 VReg inputs[] = {incoming_vreg_0, incoming_vreg_1, incoming_vreg_2, | 159 VReg inputs[] = {incoming_vreg_0, incoming_vreg_1, incoming_vreg_2, |
160 incoming_vreg_3}; | 160 incoming_vreg_3}; |
161 for (size_t i = 0; i < arraysize(inputs); ++i) { | 161 for (size_t i = 0; i < arraysize(inputs); ++i) { |
162 if (inputs[i].value_ == kNoValue) break; | 162 if (inputs[i].value_ == kNoValue) break; |
163 Extend(phi, inputs[i]); | 163 Extend(phi, inputs[i]); |
164 } | 164 } |
165 current_block_->AddPhi(phi); | 165 current_block_->AddPhi(phi); |
166 return phi; | 166 return phi; |
167 } | 167 } |
168 | 168 |
169 | 169 |
170 void InstructionSequenceTest::Extend(PhiInstruction* phi, VReg vreg) { | 170 void InstructionSequenceTest::Extend(PhiInstruction* phi, VReg vreg) { |
171 phi->Extend(zone(), vreg.value_); | 171 phi->Extend(zone(), vreg.value_); |
172 } | 172 } |
173 | 173 |
174 | 174 |
175 InstructionSequenceTest::VReg InstructionSequenceTest::DefineConstant( | 175 InstructionSequenceTest::VReg InstructionSequenceTest::DefineConstant( |
176 int32_t imm) { | 176 int32_t imm) { |
177 VReg vreg = NewReg(); | 177 VReg vreg = NewReg(); |
178 sequence()->AddConstant(vreg.value_, Constant(imm)); | 178 sequence()->AddConstant(vreg.value_, Constant(imm)); |
179 InstructionOperand* outputs[1]{ConstantOperand::Create(vreg.value_, zone())}; | 179 InstructionOperand outputs[1]{ConstantOperand(vreg.value_)}; |
180 Emit(vreg.value_, kArchNop, 1, outputs); | 180 Emit(vreg.value_, kArchNop, 1, outputs); |
181 return vreg; | 181 return vreg; |
182 } | 182 } |
183 | 183 |
184 | 184 |
185 int InstructionSequenceTest::EmitNop() { return Emit(NewIndex(), kArchNop); } | 185 int InstructionSequenceTest::EmitNop() { return Emit(NewIndex(), kArchNop); } |
186 | 186 |
187 | 187 |
188 static size_t CountInputs(size_t size, | 188 static size_t CountInputs(size_t size, |
189 InstructionSequenceTest::TestOperand* inputs) { | 189 InstructionSequenceTest::TestOperand* inputs) { |
190 size_t i = 0; | 190 size_t i = 0; |
191 for (; i < size; ++i) { | 191 for (; i < size; ++i) { |
192 if (inputs[i].type_ == InstructionSequenceTest::kInvalid) break; | 192 if (inputs[i].type_ == InstructionSequenceTest::kInvalid) break; |
193 } | 193 } |
194 return i; | 194 return i; |
195 } | 195 } |
196 | 196 |
197 | 197 |
198 int InstructionSequenceTest::EmitI(size_t input_size, TestOperand* inputs) { | 198 int InstructionSequenceTest::EmitI(size_t input_size, TestOperand* inputs) { |
199 InstructionOperand** mapped_inputs = ConvertInputs(input_size, inputs); | 199 InstructionOperand* mapped_inputs = ConvertInputs(input_size, inputs); |
200 return Emit(NewIndex(), kArchNop, 0, nullptr, input_size, mapped_inputs); | 200 return Emit(NewIndex(), kArchNop, 0, nullptr, input_size, mapped_inputs); |
201 } | 201 } |
202 | 202 |
203 | 203 |
204 int InstructionSequenceTest::EmitI(TestOperand input_op_0, | 204 int InstructionSequenceTest::EmitI(TestOperand input_op_0, |
205 TestOperand input_op_1, | 205 TestOperand input_op_1, |
206 TestOperand input_op_2, | 206 TestOperand input_op_2, |
207 TestOperand input_op_3) { | 207 TestOperand input_op_3) { |
208 TestOperand inputs[] = {input_op_0, input_op_1, input_op_2, input_op_3}; | 208 TestOperand inputs[] = {input_op_0, input_op_1, input_op_2, input_op_3}; |
209 return EmitI(CountInputs(arraysize(inputs), inputs), inputs); | 209 return EmitI(CountInputs(arraysize(inputs), inputs), inputs); |
210 } | 210 } |
211 | 211 |
212 | 212 |
213 InstructionSequenceTest::VReg InstructionSequenceTest::EmitOI( | 213 InstructionSequenceTest::VReg InstructionSequenceTest::EmitOI( |
214 TestOperand output_op, size_t input_size, TestOperand* inputs) { | 214 TestOperand output_op, size_t input_size, TestOperand* inputs) { |
215 VReg output_vreg = NewReg(); | 215 VReg output_vreg = NewReg(); |
216 InstructionOperand* outputs[1]{ConvertOutputOp(output_vreg, output_op)}; | 216 InstructionOperand outputs[1]{ConvertOutputOp(output_vreg, output_op)}; |
217 InstructionOperand** mapped_inputs = ConvertInputs(input_size, inputs); | 217 InstructionOperand* mapped_inputs = ConvertInputs(input_size, inputs); |
218 Emit(output_vreg.value_, kArchNop, 1, outputs, input_size, mapped_inputs); | 218 Emit(output_vreg.value_, kArchNop, 1, outputs, input_size, mapped_inputs); |
219 return output_vreg; | 219 return output_vreg; |
220 } | 220 } |
221 | 221 |
222 | 222 |
223 InstructionSequenceTest::VReg InstructionSequenceTest::EmitOI( | 223 InstructionSequenceTest::VReg InstructionSequenceTest::EmitOI( |
224 TestOperand output_op, TestOperand input_op_0, TestOperand input_op_1, | 224 TestOperand output_op, TestOperand input_op_0, TestOperand input_op_1, |
225 TestOperand input_op_2, TestOperand input_op_3) { | 225 TestOperand input_op_2, TestOperand input_op_3) { |
226 TestOperand inputs[] = {input_op_0, input_op_1, input_op_2, input_op_3}; | 226 TestOperand inputs[] = {input_op_0, input_op_1, input_op_2, input_op_3}; |
227 return EmitOI(output_op, CountInputs(arraysize(inputs), inputs), inputs); | 227 return EmitOI(output_op, CountInputs(arraysize(inputs), inputs), inputs); |
228 } | 228 } |
229 | 229 |
230 | 230 |
231 InstructionSequenceTest::VReg InstructionSequenceTest::EmitCall( | 231 InstructionSequenceTest::VReg InstructionSequenceTest::EmitCall( |
232 TestOperand output_op, size_t input_size, TestOperand* inputs) { | 232 TestOperand output_op, size_t input_size, TestOperand* inputs) { |
233 VReg output_vreg = NewReg(); | 233 VReg output_vreg = NewReg(); |
234 InstructionOperand* outputs[1]{ConvertOutputOp(output_vreg, output_op)}; | 234 InstructionOperand outputs[1]{ConvertOutputOp(output_vreg, output_op)}; |
235 CHECK(UnallocatedOperand::cast(outputs[0])->HasFixedPolicy()); | 235 CHECK(UnallocatedOperand::cast(outputs[0]).HasFixedPolicy()); |
236 InstructionOperand** mapped_inputs = ConvertInputs(input_size, inputs); | 236 InstructionOperand* mapped_inputs = ConvertInputs(input_size, inputs); |
237 Emit(output_vreg.value_, kArchCallCodeObject, 1, outputs, input_size, | 237 Emit(output_vreg.value_, kArchCallCodeObject, 1, outputs, input_size, |
238 mapped_inputs, 0, nullptr, true); | 238 mapped_inputs, 0, nullptr, true); |
239 return output_vreg; | 239 return output_vreg; |
240 } | 240 } |
241 | 241 |
242 | 242 |
243 InstructionSequenceTest::VReg InstructionSequenceTest::EmitCall( | 243 InstructionSequenceTest::VReg InstructionSequenceTest::EmitCall( |
244 TestOperand output_op, TestOperand input_op_0, TestOperand input_op_1, | 244 TestOperand output_op, TestOperand input_op_0, TestOperand input_op_1, |
245 TestOperand input_op_2, TestOperand input_op_3) { | 245 TestOperand input_op_2, TestOperand input_op_3) { |
246 TestOperand inputs[] = {input_op_0, input_op_1, input_op_2, input_op_3}; | 246 TestOperand inputs[] = {input_op_0, input_op_1, input_op_2, input_op_3}; |
247 return EmitCall(output_op, CountInputs(arraysize(inputs), inputs), inputs); | 247 return EmitCall(output_op, CountInputs(arraysize(inputs), inputs), inputs); |
248 } | 248 } |
249 | 249 |
250 | 250 |
251 const Instruction* InstructionSequenceTest::GetInstruction( | 251 const Instruction* InstructionSequenceTest::GetInstruction( |
252 int instruction_index) { | 252 int instruction_index) { |
253 auto it = instructions_.find(instruction_index); | 253 auto it = instructions_.find(instruction_index); |
254 CHECK(it != instructions_.end()); | 254 CHECK(it != instructions_.end()); |
255 return it->second; | 255 return it->second; |
256 } | 256 } |
257 | 257 |
258 | 258 |
259 int InstructionSequenceTest::EmitBranch(TestOperand input_op) { | 259 int InstructionSequenceTest::EmitBranch(TestOperand input_op) { |
260 InstructionOperand* inputs[4]{ConvertInputOp(input_op), ConvertInputOp(Imm()), | 260 InstructionOperand inputs[4]{ConvertInputOp(input_op), ConvertInputOp(Imm()), |
261 ConvertInputOp(Imm()), ConvertInputOp(Imm())}; | 261 ConvertInputOp(Imm()), ConvertInputOp(Imm())}; |
262 InstructionCode opcode = kArchJmp | FlagsModeField::encode(kFlags_branch) | | 262 InstructionCode opcode = kArchJmp | FlagsModeField::encode(kFlags_branch) | |
263 FlagsConditionField::encode(kEqual); | 263 FlagsConditionField::encode(kEqual); |
264 auto instruction = | 264 auto instruction = |
265 NewInstruction(opcode, 0, nullptr, 4, inputs)->MarkAsControl(); | 265 NewInstruction(opcode, 0, nullptr, 4, inputs)->MarkAsControl(); |
266 return AddInstruction(NewIndex(), instruction); | 266 return AddInstruction(NewIndex(), instruction); |
267 } | 267 } |
268 | 268 |
269 | 269 |
270 int InstructionSequenceTest::EmitFallThrough() { | 270 int InstructionSequenceTest::EmitFallThrough() { |
271 auto instruction = NewInstruction(kArchNop, 0, nullptr)->MarkAsControl(); | 271 auto instruction = NewInstruction(kArchNop, 0, nullptr)->MarkAsControl(); |
272 return AddInstruction(NewIndex(), instruction); | 272 return AddInstruction(NewIndex(), instruction); |
273 } | 273 } |
274 | 274 |
275 | 275 |
276 int InstructionSequenceTest::EmitJump() { | 276 int InstructionSequenceTest::EmitJump() { |
277 InstructionOperand* inputs[1]{ConvertInputOp(Imm())}; | 277 InstructionOperand inputs[1]{ConvertInputOp(Imm())}; |
278 auto instruction = | 278 auto instruction = |
279 NewInstruction(kArchJmp, 0, nullptr, 1, inputs)->MarkAsControl(); | 279 NewInstruction(kArchJmp, 0, nullptr, 1, inputs)->MarkAsControl(); |
280 return AddInstruction(NewIndex(), instruction); | 280 return AddInstruction(NewIndex(), instruction); |
281 } | 281 } |
282 | 282 |
283 | 283 |
284 Instruction* InstructionSequenceTest::NewInstruction( | 284 Instruction* InstructionSequenceTest::NewInstruction( |
285 InstructionCode code, size_t outputs_size, InstructionOperand** outputs, | 285 InstructionCode code, size_t outputs_size, InstructionOperand* outputs, |
286 size_t inputs_size, InstructionOperand** inputs, size_t temps_size, | 286 size_t inputs_size, InstructionOperand* inputs, size_t temps_size, |
287 InstructionOperand** temps) { | 287 InstructionOperand* temps) { |
288 CHECK(current_block_); | 288 CHECK(current_block_); |
289 return Instruction::New(zone(), code, outputs_size, outputs, inputs_size, | 289 return Instruction::New(zone(), code, outputs_size, outputs, inputs_size, |
290 inputs, temps_size, temps); | 290 inputs, temps_size, temps); |
291 } | 291 } |
292 | 292 |
293 | 293 |
294 InstructionOperand* InstructionSequenceTest::Unallocated( | 294 InstructionOperand InstructionSequenceTest::Unallocated( |
295 TestOperand op, UnallocatedOperand::ExtendedPolicy policy) { | 295 TestOperand op, UnallocatedOperand::ExtendedPolicy policy) { |
296 return new (zone()) UnallocatedOperand(policy, op.vreg_.value_); | 296 return UnallocatedOperand(policy, op.vreg_.value_); |
297 } | 297 } |
298 | 298 |
299 | 299 |
300 InstructionOperand* InstructionSequenceTest::Unallocated( | 300 InstructionOperand InstructionSequenceTest::Unallocated( |
301 TestOperand op, UnallocatedOperand::ExtendedPolicy policy, | 301 TestOperand op, UnallocatedOperand::ExtendedPolicy policy, |
302 UnallocatedOperand::Lifetime lifetime) { | 302 UnallocatedOperand::Lifetime lifetime) { |
303 return new (zone()) UnallocatedOperand(policy, lifetime, op.vreg_.value_); | 303 return UnallocatedOperand(policy, lifetime, op.vreg_.value_); |
304 } | 304 } |
305 | 305 |
306 | 306 |
307 InstructionOperand* InstructionSequenceTest::Unallocated( | 307 InstructionOperand InstructionSequenceTest::Unallocated( |
308 TestOperand op, UnallocatedOperand::ExtendedPolicy policy, int index) { | 308 TestOperand op, UnallocatedOperand::ExtendedPolicy policy, int index) { |
309 return new (zone()) UnallocatedOperand(policy, index, op.vreg_.value_); | 309 return UnallocatedOperand(policy, index, op.vreg_.value_); |
310 } | 310 } |
311 | 311 |
312 | 312 |
313 InstructionOperand* InstructionSequenceTest::Unallocated( | 313 InstructionOperand InstructionSequenceTest::Unallocated( |
314 TestOperand op, UnallocatedOperand::BasicPolicy policy, int index) { | 314 TestOperand op, UnallocatedOperand::BasicPolicy policy, int index) { |
315 return new (zone()) UnallocatedOperand(policy, index, op.vreg_.value_); | 315 return UnallocatedOperand(policy, index, op.vreg_.value_); |
316 } | 316 } |
317 | 317 |
318 | 318 |
319 InstructionOperand** InstructionSequenceTest::ConvertInputs( | 319 InstructionOperand* InstructionSequenceTest::ConvertInputs( |
320 size_t input_size, TestOperand* inputs) { | 320 size_t input_size, TestOperand* inputs) { |
321 InstructionOperand** mapped_inputs = | 321 InstructionOperand* mapped_inputs = |
322 zone()->NewArray<InstructionOperand*>(static_cast<int>(input_size)); | 322 zone()->NewArray<InstructionOperand>(static_cast<int>(input_size)); |
323 for (size_t i = 0; i < input_size; ++i) { | 323 for (size_t i = 0; i < input_size; ++i) { |
324 mapped_inputs[i] = ConvertInputOp(inputs[i]); | 324 mapped_inputs[i] = ConvertInputOp(inputs[i]); |
325 } | 325 } |
326 return mapped_inputs; | 326 return mapped_inputs; |
327 } | 327 } |
328 | 328 |
329 | 329 |
330 InstructionOperand* InstructionSequenceTest::ConvertInputOp(TestOperand op) { | 330 InstructionOperand InstructionSequenceTest::ConvertInputOp(TestOperand op) { |
331 if (op.type_ == kImmediate) { | 331 if (op.type_ == kImmediate) { |
332 CHECK_EQ(op.vreg_.value_, kNoValue); | 332 CHECK_EQ(op.vreg_.value_, kNoValue); |
333 return ImmediateOperand::Create(op.value_, zone()); | 333 return ImmediateOperand(op.value_); |
334 } | 334 } |
335 CHECK_NE(op.vreg_.value_, kNoValue); | 335 CHECK_NE(op.vreg_.value_, kNoValue); |
336 switch (op.type_) { | 336 switch (op.type_) { |
337 case kNone: | 337 case kNone: |
338 return Unallocated(op, UnallocatedOperand::NONE, | 338 return Unallocated(op, UnallocatedOperand::NONE, |
339 UnallocatedOperand::USED_AT_START); | 339 UnallocatedOperand::USED_AT_START); |
340 case kUnique: | 340 case kUnique: |
341 return Unallocated(op, UnallocatedOperand::NONE); | 341 return Unallocated(op, UnallocatedOperand::NONE); |
342 case kUniqueRegister: | 342 case kUniqueRegister: |
343 return Unallocated(op, UnallocatedOperand::MUST_HAVE_REGISTER); | 343 return Unallocated(op, UnallocatedOperand::MUST_HAVE_REGISTER); |
344 case kRegister: | 344 case kRegister: |
345 return Unallocated(op, UnallocatedOperand::MUST_HAVE_REGISTER, | 345 return Unallocated(op, UnallocatedOperand::MUST_HAVE_REGISTER, |
346 UnallocatedOperand::USED_AT_START); | 346 UnallocatedOperand::USED_AT_START); |
347 case kFixedRegister: | 347 case kFixedRegister: |
348 CHECK(0 <= op.value_ && op.value_ < num_general_registers_); | 348 CHECK(0 <= op.value_ && op.value_ < num_general_registers_); |
349 return Unallocated(op, UnallocatedOperand::FIXED_REGISTER, op.value_); | 349 return Unallocated(op, UnallocatedOperand::FIXED_REGISTER, op.value_); |
350 case kFixedSlot: | 350 case kFixedSlot: |
351 return Unallocated(op, UnallocatedOperand::FIXED_SLOT, op.value_); | 351 return Unallocated(op, UnallocatedOperand::FIXED_SLOT, op.value_); |
352 default: | 352 default: |
353 break; | 353 break; |
354 } | 354 } |
355 CHECK(false); | 355 CHECK(false); |
356 return NULL; | 356 return InstructionOperand(); |
357 } | 357 } |
358 | 358 |
359 | 359 |
360 InstructionOperand* InstructionSequenceTest::ConvertOutputOp(VReg vreg, | 360 InstructionOperand InstructionSequenceTest::ConvertOutputOp(VReg vreg, |
361 TestOperand op) { | 361 TestOperand op) { |
362 CHECK_EQ(op.vreg_.value_, kNoValue); | 362 CHECK_EQ(op.vreg_.value_, kNoValue); |
363 op.vreg_ = vreg; | 363 op.vreg_ = vreg; |
364 switch (op.type_) { | 364 switch (op.type_) { |
365 case kSameAsFirst: | 365 case kSameAsFirst: |
366 return Unallocated(op, UnallocatedOperand::SAME_AS_FIRST_INPUT); | 366 return Unallocated(op, UnallocatedOperand::SAME_AS_FIRST_INPUT); |
367 case kRegister: | 367 case kRegister: |
368 return Unallocated(op, UnallocatedOperand::MUST_HAVE_REGISTER); | 368 return Unallocated(op, UnallocatedOperand::MUST_HAVE_REGISTER); |
369 case kFixedSlot: | 369 case kFixedSlot: |
370 return Unallocated(op, UnallocatedOperand::FIXED_SLOT, op.value_); | 370 return Unallocated(op, UnallocatedOperand::FIXED_SLOT, op.value_); |
371 case kFixedRegister: | 371 case kFixedRegister: |
372 CHECK(0 <= op.value_ && op.value_ < num_general_registers_); | 372 CHECK(0 <= op.value_ && op.value_ < num_general_registers_); |
373 return Unallocated(op, UnallocatedOperand::FIXED_REGISTER, op.value_); | 373 return Unallocated(op, UnallocatedOperand::FIXED_REGISTER, op.value_); |
374 default: | 374 default: |
375 break; | 375 break; |
376 } | 376 } |
377 CHECK(false); | 377 CHECK(false); |
378 return NULL; | 378 return InstructionOperand(); |
379 } | 379 } |
380 | 380 |
381 | 381 |
382 InstructionBlock* InstructionSequenceTest::NewBlock() { | 382 InstructionBlock* InstructionSequenceTest::NewBlock() { |
383 CHECK(current_block_ == nullptr); | 383 CHECK(current_block_ == nullptr); |
384 auto block_id = BasicBlock::Id::FromSize(instruction_blocks_.size()); | 384 auto block_id = BasicBlock::Id::FromSize(instruction_blocks_.size()); |
385 Rpo rpo = Rpo::FromInt(block_id.ToInt()); | 385 Rpo rpo = Rpo::FromInt(block_id.ToInt()); |
386 Rpo loop_header = Rpo::Invalid(); | 386 Rpo loop_header = Rpo::Invalid(); |
387 Rpo loop_end = Rpo::Invalid(); | 387 Rpo loop_end = Rpo::Invalid(); |
388 if (!loop_blocks_.empty()) { | 388 if (!loop_blocks_.empty()) { |
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438 CHECK(target_block_offset < instruction_blocks_.size()); | 438 CHECK(target_block_offset < instruction_blocks_.size()); |
439 auto block = instruction_blocks_[block_offset]; | 439 auto block = instruction_blocks_[block_offset]; |
440 auto target = instruction_blocks_[target_block_offset]; | 440 auto target = instruction_blocks_[target_block_offset]; |
441 block->successors().push_back(target->rpo_number()); | 441 block->successors().push_back(target->rpo_number()); |
442 target->predecessors().push_back(block->rpo_number()); | 442 target->predecessors().push_back(block->rpo_number()); |
443 } | 443 } |
444 | 444 |
445 | 445 |
446 int InstructionSequenceTest::Emit(int instruction_index, InstructionCode code, | 446 int InstructionSequenceTest::Emit(int instruction_index, InstructionCode code, |
447 size_t outputs_size, | 447 size_t outputs_size, |
448 InstructionOperand** outputs, | 448 InstructionOperand* outputs, |
449 size_t inputs_size, | 449 size_t inputs_size, |
450 InstructionOperand** inputs, | 450 InstructionOperand* inputs, size_t temps_size, |
451 size_t temps_size, InstructionOperand** temps, | 451 InstructionOperand* temps, bool is_call) { |
452 bool is_call) { | |
453 auto instruction = NewInstruction(code, outputs_size, outputs, inputs_size, | 452 auto instruction = NewInstruction(code, outputs_size, outputs, inputs_size, |
454 inputs, temps_size, temps); | 453 inputs, temps_size, temps); |
455 if (is_call) instruction->MarkAsCall(); | 454 if (is_call) instruction->MarkAsCall(); |
456 return AddInstruction(instruction_index, instruction); | 455 return AddInstruction(instruction_index, instruction); |
457 } | 456 } |
458 | 457 |
459 | 458 |
460 int InstructionSequenceTest::AddInstruction(int instruction_index, | 459 int InstructionSequenceTest::AddInstruction(int instruction_index, |
461 Instruction* instruction) { | 460 Instruction* instruction) { |
462 sequence()->AddInstruction(instruction); | 461 sequence()->AddInstruction(instruction); |
463 return instruction_index; | 462 return instruction_index; |
464 } | 463 } |
465 | 464 |
466 } // namespace compiler | 465 } // namespace compiler |
467 } // namespace internal | 466 } // namespace internal |
468 } // namespace v8 | 467 } // namespace v8 |
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