Undo unnecessary changes to ARM assembler.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 2692 matching lines @@
   } else {
     ASSERT(version == ARMv7);
     const uint16_t value_low = Utils::Low16Bits(value);
     const uint16_t value_high = Utils::High16Bits(value);
     movw(rd, value_low, cond);
     movt(rd, value_high, cond);
   }
 }
 
 
+void Assembler::LoadDecodableImmediate(
+    Register rd, int32_t value, Condition cond) {
+  const ARMVersion version = TargetCPUFeatures::arm_version();
+  if ((version == ARMv5TE) || (version == ARMv6)) {
+    LoadPatchableImmediate(rd, value, cond);
+  } else {
+    ASSERT(version == ARMv7);
+    movw(rd, Utils::Low16Bits(value), cond);
+    const uint16_t value_high = Utils::High16Bits(value);
+    if (value_high != 0) {
+      movt(rd, value_high, cond);
+    }
+  }
+}
+
+
 void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
   Operand o;
   if (Operand::CanHold(value, &o)) {
     mov(rd, o, cond);
   } else if (Operand::CanHold(~value, &o)) {
     mvn(rd, o, cond);
   } else {
-    LoadPatchableImmediate(rd, value, cond);
+    LoadDecodableImmediate(rd, value, cond);
   }
 }
 
 
 void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) {
   if (!vmovs(sd, value, cond)) {
     const DRegister dd = static_cast<DRegister>(sd >> 1);
     const int index = sd & 1;
     LoadImmediate(IP, bit_cast<int32_t, float>(value), cond);
     vmovdr(dd, index, IP, cond);
@@ skipping 265 matching lines @@
     sub(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
     if (Operand::CanHold(~value, &o)) {
       mvn(IP, o, cond);
       add(rd, rn, Operand(IP), cond);
     } else if (Operand::CanHold(~(-value), &o)) {
       mvn(IP, o, cond);
       sub(rd, rn, Operand(IP), cond);
     } else {
-      LoadPatchableImmediate(IP, value, cond);
+      LoadDecodableImmediate(IP, value, cond);
       add(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
                                      Condition cond) {
   Operand o;
   if (Operand::CanHold(value, &o)) {
     // Handles value == kMinInt32.
     adds(rd, rn, o, cond);
   } else if (Operand::CanHold(-value, &o)) {
     ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
     subs(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
     if (Operand::CanHold(~value, &o)) {
       mvn(IP, o, cond);
       adds(rd, rn, Operand(IP), cond);
     } else if (Operand::CanHold(~(-value), &o)) {
       ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
       mvn(IP, o, cond);
       subs(rd, rn, Operand(IP), cond);
     } else {
-      LoadPatchableImmediate(IP, value, cond);
+      LoadDecodableImmediate(IP, value, cond);
       adds(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
                                     Condition cond) {
   Operand o;
   if (Operand::CanHold(value, &o)) {
     // Handles value == kMinInt32.
     subs(rd, rn, o, cond);
   } else if (Operand::CanHold(-value, &o)) {
     ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
     adds(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
     if (Operand::CanHold(~value, &o)) {
       mvn(IP, o, cond);
       subs(rd, rn, Operand(IP), cond);
     } else if (Operand::CanHold(~(-value), &o)) {
       ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
       mvn(IP, o, cond);
       adds(rd, rn, Operand(IP), cond);
     } else {
-      LoadPatchableImmediate(IP, value, cond);
+      LoadDecodableImmediate(IP, value, cond);
       subs(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
                              Condition cond) {
   Operand o;
   if (Operand::CanHold(imm, &o)) {
@@ skipping 546 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM