Subzero: Use a "known" version of clang-format.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 43 matching lines @@
 const struct TableFcmp_ {
   uint32_t Default;
   bool SwapScalarOperands;
   CondX86::BrCond C1, C2;
   bool SwapVectorOperands;
   CondX86::CmppsCond Predicate;
 } TableFcmp[] = {
 #define X(val, dflt, swapS, C1, C2, swapV, pred)                               \
   { dflt, swapS, CondX86::C1, CondX86::C2, swapV, CondX86::pred }              \
   ,
-    FCMPX8632_TABLE
+      FCMPX8632_TABLE
 #undef X
-  };
+};
 const size_t TableFcmpSize = llvm::array_lengthof(TableFcmp);
 
 // The following table summarizes the logic for lowering the icmp instruction
 // for i32 and narrower types.  Each icmp condition has a clear mapping to an
 // x86 conditional branch instruction.
 
 const struct TableIcmp32_ {
   CondX86::BrCond Mapping;
 } TableIcmp32[] = {
 #define X(val, C_32, C1_64, C2_64, C3_64)                                      \
   { CondX86::C_32 }                                                            \
   ,
-    ICMPX8632_TABLE
+      ICMPX8632_TABLE
 #undef X
-  };
+};
 const size_t TableIcmp32Size = llvm::array_lengthof(TableIcmp32);
 
 // The following table summarizes the logic for lowering the icmp instruction
 // for the i64 type.  For Eq and Ne, two separate 32-bit comparisons and
 // conditional branches are needed.  For the other conditions, three separate
 // conditional branches are needed.
 const struct TableIcmp64_ {
   CondX86::BrCond C1, C2, C3;
 } TableIcmp64[] = {
 #define X(val, C_32, C1_64, C2_64, C3_64)                                      \
   { CondX86::C1_64, CondX86::C2_64, CondX86::C3_64 }                           \
   ,
-    ICMPX8632_TABLE
+      ICMPX8632_TABLE
 #undef X
-  };
+};
 const size_t TableIcmp64Size = llvm::array_lengthof(TableIcmp64);
 
 CondX86::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
   size_t Index = static_cast<size_t>(Cond);
   assert(Index < TableIcmp32Size);
   return TableIcmp32[Index].Mapping;
 }
 
 const struct TableTypeX8632Attributes_ {
   Type InVectorElementType;
 } TableTypeX8632Attributes[] = {
 #define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
   { elementty }                                                                \
   ,
-    ICETYPEX8632_TABLE
+      ICETYPEX8632_TABLE
 #undef X
-  };
+};
 const size_t TableTypeX8632AttributesSize =
     llvm::array_lengthof(TableTypeX8632Attributes);
 
 // Return the type which the elements of the vector have in the X86
 // representation of the vector.
 Type getInVectorElementType(Type Ty) {
   assert(isVectorType(Ty));
   size_t Index = static_cast<size_t>(Ty);
   (void)Index;
   assert(Index < TableTypeX8632AttributesSize);
@@ skipping 24 matching lines @@
 }
 
 // Value is in bytes. Return Value adjusted to the next highest multiple
 // of the stack alignment.
 uint32_t applyStackAlignment(uint32_t Value) {
   return applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
 }
 
 // Instruction set options
 namespace cl = ::llvm::cl;
-cl::opt<TargetX8632::X86InstructionSet>
-CLInstructionSet("mattr", cl::desc("X86 target attributes"),
-                 cl::init(TargetX8632::SSE2),
-                 cl::values(clEnumValN(TargetX8632::SSE2, "sse2",
-                                       "Enable SSE2 instructions (default)"),
-                            clEnumValN(TargetX8632::SSE4_1, "sse4.1",
-                                       "Enable SSE 4.1 instructions"),
-                            clEnumValEnd));
+cl::opt<TargetX8632::X86InstructionSet> CLInstructionSet(
+    "mattr", cl::desc("X86 target attributes"), cl::init(TargetX8632::SSE2),
+    cl::values(clEnumValN(TargetX8632::SSE2, "sse2",
+                          "Enable SSE2 instructions (default)"),
+               clEnumValN(TargetX8632::SSE4_1, "sse4.1",
+                          "Enable SSE 4.1 instructions"),
+               clEnumValEnd));
 
 // In some cases, there are x-macros tables for both high-level and
 // low-level instructions/operands that use the same enum key value.
 // The tables are kept separate to maintain a proper separation
 // between abstraction layers.  There is a risk that the tables could
 // get out of sync if enum values are reordered or if entries are
 // added or deleted.  The following dummy namespaces use
 // static_asserts to ensure everything is kept in sync.
 
 // Validate the enum values in FCMPX8632_TABLE.
@@ skipping 271 matching lines @@
   if (InstX8632Br *Br = llvm::dyn_cast<InstX8632Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
 IceString TargetX8632::RegNames[] = {
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name,
-  REGX8632_TABLE
+    REGX8632_TABLE
 #undef X
 };
 
 Variable *TargetX8632::getPhysicalRegister(SizeT RegNum, Type Ty) {
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(RegX8632::Reg_NUM);
   assert(RegNum < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
@@ skipping 10 matching lines @@
   }
   return Reg;
 }
 
 IceString TargetX8632::getRegName(SizeT RegNum, Type Ty) const {
   assert(RegNum < RegX8632::Reg_NUM);
   static IceString RegNames8[] = {
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name8,
-    REGX8632_TABLE
+      REGX8632_TABLE
 #undef X
   };
   static IceString RegNames16[] = {
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name16,
-    REGX8632_TABLE
+      REGX8632_TABLE
 #undef X
   };
   switch (Ty) {
   case IceType_i1:
   case IceType_i8:
     return RegNames8[RegNum];
   case IceType_i16:
     return RegNames16[RegNum];
   default:
     return RegNames[RegNum];
@@ skipping 2249 matching lines @@
     //
     // insertelement into index 2 (result is stored in T):
     //   T := SourceVectRM
     //   ElementR := ElementR[0, 0] T[0, 3]
     //   T := T[0, 1] ElementR[0, 3]
     //
     // insertelement into index 3 (result is stored in T):
     //   T := SourceVectRM
     //   ElementR := ElementR[0, 0] T[0, 2]
     //   T := T[0, 1] ElementR[3, 0]
-    const unsigned char Mask1[3] = { 0, 192, 128 };
-    const unsigned char Mask2[3] = { 227, 196, 52 };
+    const unsigned char Mask1[3] = {0, 192, 128};
+    const unsigned char Mask2[3] = {227, 196, 52};
 
     Constant *Mask1Constant = Ctx->getConstantInt32(Mask1[Index - 1]);
     Constant *Mask2Constant = Ctx->getConstantInt32(Mask2[Index - 1]);
 
     if (Index == 1) {
       _shufps(ElementR, SourceVectRM, Mask1Constant);
       _shufps(ElementR, SourceVectRM, Mask2Constant);
       _movp(Inst->getDest(), ElementR);
     } else {
       Variable *T = makeReg(Ty);
@@ skipping 22 matching lines @@
     Variable *T = makeReg(Ty);
     _movp(T, Slot);
     _movp(Inst->getDest(), T);
   }
 }
 
 void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
   switch (Instr->getIntrinsicInfo().ID) {
   case Intrinsics::AtomicCmpxchg: {
     if (!Intrinsics::VerifyMemoryOrder(
-             llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
+            llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
       Func->setError("Unexpected memory ordering (success) for AtomicCmpxchg");
       return;
     }
     if (!Intrinsics::VerifyMemoryOrder(
-             llvm::cast<ConstantInteger32>(Instr->getArg(4))->getValue())) {
+            llvm::cast<ConstantInteger32>(Instr->getArg(4))->getValue())) {
       Func->setError("Unexpected memory ordering (failure) for AtomicCmpxchg");
       return;
     }
     Variable *DestPrev = Instr->getDest();
     Operand *PtrToMem = Instr->getArg(0);
     Operand *Expected = Instr->getArg(1);
     Operand *Desired = Instr->getArg(2);
     if (tryOptimizedCmpxchgCmpBr(DestPrev, PtrToMem, Expected, Desired))
       return;
     lowerAtomicCmpxchg(DestPrev, PtrToMem, Expected, Desired);
     return;
   }
   case Intrinsics::AtomicFence:
     if (!Intrinsics::VerifyMemoryOrder(
-             llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue())) {
+            llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue())) {
       Func->setError("Unexpected memory ordering for AtomicFence");
       return;
     }
     _mfence();
     return;
   case Intrinsics::AtomicFenceAll:
     // NOTE: FenceAll should prevent and load/store from being moved
     // across the fence (both atomic and non-atomic). The InstX8632Mfence
     // instruction is currently marked coarsely as "HasSideEffects".
     _mfence();
@@ skipping 25 matching lines @@
       return;
     }
     // The PNaCl ABI requires the byte size to be a compile-time constant.
     Func->setError("AtomicIsLockFree byte size should be compile-time const");
     return;
   }
   case Intrinsics::AtomicLoad: {
     // We require the memory address to be naturally aligned.
     // Given that is the case, then normal loads are atomic.
     if (!Intrinsics::VerifyMemoryOrder(
-             llvm::cast<ConstantInteger32>(Instr->getArg(1))->getValue())) {
+            llvm::cast<ConstantInteger32>(Instr->getArg(1))->getValue())) {
       Func->setError("Unexpected memory ordering for AtomicLoad");
       return;
     }
     Variable *Dest = Instr->getDest();
     if (Dest->getType() == IceType_i64) {
       // Follow what GCC does and use a movq instead of what lowerLoad()
       // normally does (split the load into two).
       // Thus, this skips load/arithmetic op folding. Load/arithmetic folding
       // can't happen anyway, since this is x86-32 and integer arithmetic only
       // happens on 32-bit quantities.
@@ skipping 12 matching lines @@
     lowerLoad(Load);
     // Make sure the atomic load isn't elided when unused, by adding a FakeUse.
     // Since lowerLoad may fuse the load w/ an arithmetic instruction,
     // insert the FakeUse on the last-inserted instruction's dest.
     Context.insert(
         InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
     return;
   }
   case Intrinsics::AtomicRMW:
     if (!Intrinsics::VerifyMemoryOrder(
-             llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
+            llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
       Func->setError("Unexpected memory ordering for AtomicRMW");
       return;
     }
     lowerAtomicRMW(Instr->getDest(),
                    static_cast<uint32_t>(llvm::cast<ConstantInteger32>(
-                       Instr->getArg(0))->getValue()),
+                                             Instr->getArg(0))->getValue()),
                    Instr->getArg(1), Instr->getArg(2));
     return;
   case Intrinsics::AtomicStore: {
     if (!Intrinsics::VerifyMemoryOrder(
-             llvm::cast<ConstantInteger32>(Instr->getArg(2))->getValue())) {
+            llvm::cast<ConstantInteger32>(Instr->getArg(2))->getValue())) {
       Func->setError("Unexpected memory ordering for AtomicStore");
       return;
     }
     // We require the memory address to be naturally aligned.
     // Given that is the case, then normal stores are atomic.
     // Add a fence after the store to make it visible.
     Operand *Value = Instr->getArg(0);
     Operand *Ptr = Instr->getArg(1);
     if (Value->getType() == IceType_i64) {
       // Use a movq instead of what lowerStore() normally does
@@ skipping 1640 matching lines @@
     return;
 
   Ostream &Str = Ctx->getStrEmit();
 
   const VariableDeclaration::InitializerListType &Initializers =
       Var.getInitializers();
 
   // If external and not initialized, this must be a cross test.
   // Don't generate a declaration for such cases.
   bool IsExternal = Var.isExternal() || Ctx->getFlags().DisableInternal;
-  if (IsExternal && !Var.hasInitializer()) return;
+  if (IsExternal && !Var.hasInitializer())
+    return;
 
   bool HasNonzeroInitializer = Var.hasNonzeroInitializer();
   bool IsConstant = Var.getIsConstant();
   uint32_t Align = Var.getAlignment();
   SizeT Size = Var.getNumBytes();
   IceString MangledName = Var.mangleName(Ctx);
   IceString SectionSuffix = "";
   if (Ctx->getFlags().DataSections)
     SectionSuffix = "." + MangledName;
 
@@ skipping 120 matching lines @@
     Writer->writeConstantPool<ConstantFloat>(IceType_f32);
     Writer->writeConstantPool<ConstantDouble>(IceType_f64);
   } else {
     OstreamLocker L(Ctx);
     emitConstantPool<PoolTypeConverter<float>>(Ctx);
     emitConstantPool<PoolTypeConverter<double>>(Ctx);
   }
 }
 
 } // end of namespace Ice