OLD | NEW |
1 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===// | 1 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file implements the InstX8632 and OperandX8632 classes, | 10 // This file implements the InstX8632 and OperandX8632 classes, |
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27 namespace { | 27 namespace { |
28 | 28 |
29 const struct InstX8632BrAttributes_ { | 29 const struct InstX8632BrAttributes_ { |
30 CondX86::BrCond Opposite; | 30 CondX86::BrCond Opposite; |
31 const char *DisplayString; | 31 const char *DisplayString; |
32 const char *EmitString; | 32 const char *EmitString; |
33 } InstX8632BrAttributes[] = { | 33 } InstX8632BrAttributes[] = { |
34 #define X(tag, encode, opp, dump, emit) \ | 34 #define X(tag, encode, opp, dump, emit) \ |
35 { CondX86::opp, dump, emit } \ | 35 { CondX86::opp, dump, emit } \ |
36 , | 36 , |
37 ICEINSTX8632BR_TABLE | 37 ICEINSTX8632BR_TABLE |
38 #undef X | 38 #undef X |
39 }; | 39 }; |
40 | 40 |
41 const struct InstX8632CmppsAttributes_ { | 41 const struct InstX8632CmppsAttributes_ { |
42 const char *EmitString; | 42 const char *EmitString; |
43 } InstX8632CmppsAttributes[] = { | 43 } InstX8632CmppsAttributes[] = { |
44 #define X(tag, emit) \ | 44 #define X(tag, emit) \ |
45 { emit } \ | 45 { emit } \ |
46 , | 46 , |
47 ICEINSTX8632CMPPS_TABLE | 47 ICEINSTX8632CMPPS_TABLE |
48 #undef X | 48 #undef X |
49 }; | 49 }; |
50 | 50 |
51 const struct TypeX8632Attributes_ { | 51 const struct TypeX8632Attributes_ { |
52 const char *CvtString; // i (integer), s (single FP), d (double FP) | 52 const char *CvtString; // i (integer), s (single FP), d (double FP) |
53 const char *SdSsString; // ss, sd, or <blank> | 53 const char *SdSsString; // ss, sd, or <blank> |
54 const char *PackString; // b, w, d, or <blank> | 54 const char *PackString; // b, w, d, or <blank> |
55 const char *WidthString; // b, w, l, q, or <blank> | 55 const char *WidthString; // b, w, l, q, or <blank> |
56 const char *FldString; // s, l, or <blank> | 56 const char *FldString; // s, l, or <blank> |
57 } TypeX8632Attributes[] = { | 57 } TypeX8632Attributes[] = { |
58 #define X(tag, elementty, cvt, sdss, pack, width, fld) \ | 58 #define X(tag, elementty, cvt, sdss, pack, width, fld) \ |
59 { cvt, sdss, pack, width, fld } \ | 59 { cvt, sdss, pack, width, fld } \ |
60 , | 60 , |
61 ICETYPEX8632_TABLE | 61 ICETYPEX8632_TABLE |
62 #undef X | 62 #undef X |
63 }; | 63 }; |
64 | 64 |
65 const char *InstX8632SegmentRegNames[] = { | 65 const char *InstX8632SegmentRegNames[] = { |
66 #define X(val, name, prefix) name, | 66 #define X(val, name, prefix) name, |
67 SEG_REGX8632_TABLE | 67 SEG_REGX8632_TABLE |
68 #undef X | 68 #undef X |
69 }; | 69 }; |
70 | 70 |
71 uint8_t InstX8632SegmentPrefixes[] = { | 71 uint8_t InstX8632SegmentPrefixes[] = { |
72 #define X(val, name, prefix) prefix, | 72 #define X(val, name, prefix) prefix, |
73 SEG_REGX8632_TABLE | 73 SEG_REGX8632_TABLE |
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893 template <> const char *InstX8632Pinsr::Opcode = "pinsr"; | 893 template <> const char *InstX8632Pinsr::Opcode = "pinsr"; |
894 template <> const char *InstX8632Blendvps::Opcode = "blendvps"; | 894 template <> const char *InstX8632Blendvps::Opcode = "blendvps"; |
895 template <> const char *InstX8632Pblendvb::Opcode = "pblendvb"; | 895 template <> const char *InstX8632Pblendvb::Opcode = "pblendvb"; |
896 // Three address ops | 896 // Three address ops |
897 template <> const char *InstX8632Pextr::Opcode = "pextr"; | 897 template <> const char *InstX8632Pextr::Opcode = "pextr"; |
898 template <> const char *InstX8632Pshufd::Opcode = "pshufd"; | 898 template <> const char *InstX8632Pshufd::Opcode = "pshufd"; |
899 | 899 |
900 // Inplace GPR ops | 900 // Inplace GPR ops |
901 template <> | 901 template <> |
902 const x86::AssemblerX86::GPREmitterOneOp InstX8632Bswap::Emitter = { | 902 const x86::AssemblerX86::GPREmitterOneOp InstX8632Bswap::Emitter = { |
903 &x86::AssemblerX86::bswap, nullptr /* only a reg form exists */}; | 903 &x86::AssemblerX86::bswap, nullptr /* only a reg form exists */ |
| 904 }; |
904 template <> | 905 template <> |
905 const x86::AssemblerX86::GPREmitterOneOp InstX8632Neg::Emitter = { | 906 const x86::AssemblerX86::GPREmitterOneOp InstX8632Neg::Emitter = { |
906 &x86::AssemblerX86::neg, &x86::AssemblerX86::neg}; | 907 &x86::AssemblerX86::neg, &x86::AssemblerX86::neg}; |
907 | 908 |
908 // Unary GPR ops | 909 // Unary GPR ops |
909 template <> | 910 template <> |
910 const x86::AssemblerX86::GPREmitterRegOp InstX8632Bsf::Emitter = { | 911 const x86::AssemblerX86::GPREmitterRegOp InstX8632Bsf::Emitter = { |
911 &x86::AssemblerX86::bsf, &x86::AssemblerX86::bsf, nullptr}; | 912 &x86::AssemblerX86::bsf, &x86::AssemblerX86::bsf, nullptr}; |
912 template <> | 913 template <> |
913 const x86::AssemblerX86::GPREmitterRegOp InstX8632Bsr::Emitter = { | 914 const x86::AssemblerX86::GPREmitterRegOp InstX8632Bsr::Emitter = { |
914 &x86::AssemblerX86::bsr, &x86::AssemblerX86::bsr, nullptr}; | 915 &x86::AssemblerX86::bsr, &x86::AssemblerX86::bsr, nullptr}; |
915 template <> | 916 template <> |
916 const x86::AssemblerX86::GPREmitterRegOp InstX8632Lea::Emitter = { | 917 const x86::AssemblerX86::GPREmitterRegOp InstX8632Lea::Emitter = { |
917 /* reg/reg and reg/imm are illegal */ nullptr, &x86::AssemblerX86::lea, | 918 /* reg/reg and reg/imm are illegal */ nullptr, &x86::AssemblerX86::lea, |
918 nullptr}; | 919 nullptr}; |
919 template <> | 920 template <> |
920 const x86::AssemblerX86::GPREmitterRegOp InstX8632Movsx::Emitter = { | 921 const x86::AssemblerX86::GPREmitterRegOp InstX8632Movsx::Emitter = { |
921 &x86::AssemblerX86::movsx, &x86::AssemblerX86::movsx, nullptr}; | 922 &x86::AssemblerX86::movsx, &x86::AssemblerX86::movsx, nullptr}; |
922 template <> | 923 template <> |
923 const x86::AssemblerX86::GPREmitterRegOp InstX8632Movzx::Emitter = { | 924 const x86::AssemblerX86::GPREmitterRegOp InstX8632Movzx::Emitter = { |
924 &x86::AssemblerX86::movzx, &x86::AssemblerX86::movzx, nullptr}; | 925 &x86::AssemblerX86::movzx, &x86::AssemblerX86::movzx, nullptr}; |
925 | 926 |
926 // Unary XMM ops | 927 // Unary XMM ops |
927 template <> | 928 template <> |
928 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Sqrtss::Emitter = { | 929 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Sqrtss::Emitter = { |
929 &x86::AssemblerX86::sqrtss, &x86::AssemblerX86::sqrtss | 930 &x86::AssemblerX86::sqrtss, &x86::AssemblerX86::sqrtss}; |
930 }; | |
931 | 931 |
932 // Binary GPR ops | 932 // Binary GPR ops |
933 template <> | 933 template <> |
934 const x86::AssemblerX86::GPREmitterRegOp InstX8632Add::Emitter = { | 934 const x86::AssemblerX86::GPREmitterRegOp InstX8632Add::Emitter = { |
935 &x86::AssemblerX86::add, &x86::AssemblerX86::add, &x86::AssemblerX86::add}; | 935 &x86::AssemblerX86::add, &x86::AssemblerX86::add, &x86::AssemblerX86::add}; |
936 template <> | 936 template <> |
937 const x86::AssemblerX86::GPREmitterRegOp InstX8632Adc::Emitter = { | 937 const x86::AssemblerX86::GPREmitterRegOp InstX8632Adc::Emitter = { |
938 &x86::AssemblerX86::adc, &x86::AssemblerX86::adc, &x86::AssemblerX86::adc}; | 938 &x86::AssemblerX86::adc, &x86::AssemblerX86::adc, &x86::AssemblerX86::adc}; |
939 template <> | 939 template <> |
940 const x86::AssemblerX86::GPREmitterRegOp InstX8632And::Emitter = { | 940 const x86::AssemblerX86::GPREmitterRegOp InstX8632And::Emitter = { |
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962 template <> | 962 template <> |
963 const x86::AssemblerX86::GPREmitterShiftOp InstX8632Shl::Emitter = { | 963 const x86::AssemblerX86::GPREmitterShiftOp InstX8632Shl::Emitter = { |
964 &x86::AssemblerX86::shl, &x86::AssemblerX86::shl}; | 964 &x86::AssemblerX86::shl, &x86::AssemblerX86::shl}; |
965 template <> | 965 template <> |
966 const x86::AssemblerX86::GPREmitterShiftOp InstX8632Shr::Emitter = { | 966 const x86::AssemblerX86::GPREmitterShiftOp InstX8632Shr::Emitter = { |
967 &x86::AssemblerX86::shr, &x86::AssemblerX86::shr}; | 967 &x86::AssemblerX86::shr, &x86::AssemblerX86::shr}; |
968 | 968 |
969 // Binary XMM ops | 969 // Binary XMM ops |
970 template <> | 970 template <> |
971 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Addss::Emitter = { | 971 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Addss::Emitter = { |
972 &x86::AssemblerX86::addss, &x86::AssemblerX86::addss | 972 &x86::AssemblerX86::addss, &x86::AssemblerX86::addss}; |
973 }; | |
974 template <> | 973 template <> |
975 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Addps::Emitter = { | 974 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Addps::Emitter = { |
976 &x86::AssemblerX86::addps, &x86::AssemblerX86::addps | 975 &x86::AssemblerX86::addps, &x86::AssemblerX86::addps}; |
977 }; | |
978 template <> | 976 template <> |
979 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Divss::Emitter = { | 977 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Divss::Emitter = { |
980 &x86::AssemblerX86::divss, &x86::AssemblerX86::divss | 978 &x86::AssemblerX86::divss, &x86::AssemblerX86::divss}; |
981 }; | |
982 template <> | 979 template <> |
983 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Divps::Emitter = { | 980 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Divps::Emitter = { |
984 &x86::AssemblerX86::divps, &x86::AssemblerX86::divps | 981 &x86::AssemblerX86::divps, &x86::AssemblerX86::divps}; |
985 }; | |
986 template <> | 982 template <> |
987 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Mulss::Emitter = { | 983 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Mulss::Emitter = { |
988 &x86::AssemblerX86::mulss, &x86::AssemblerX86::mulss | 984 &x86::AssemblerX86::mulss, &x86::AssemblerX86::mulss}; |
989 }; | |
990 template <> | 985 template <> |
991 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Mulps::Emitter = { | 986 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Mulps::Emitter = { |
992 &x86::AssemblerX86::mulps, &x86::AssemblerX86::mulps | 987 &x86::AssemblerX86::mulps, &x86::AssemblerX86::mulps}; |
993 }; | |
994 template <> | 988 template <> |
995 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Padd::Emitter = { | 989 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Padd::Emitter = { |
996 &x86::AssemblerX86::padd, &x86::AssemblerX86::padd | 990 &x86::AssemblerX86::padd, &x86::AssemblerX86::padd}; |
997 }; | |
998 template <> | 991 template <> |
999 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pand::Emitter = { | 992 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pand::Emitter = { |
1000 &x86::AssemblerX86::pand, &x86::AssemblerX86::pand | 993 &x86::AssemblerX86::pand, &x86::AssemblerX86::pand}; |
1001 }; | |
1002 template <> | 994 template <> |
1003 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pandn::Emitter = { | 995 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pandn::Emitter = { |
1004 &x86::AssemblerX86::pandn, &x86::AssemblerX86::pandn | 996 &x86::AssemblerX86::pandn, &x86::AssemblerX86::pandn}; |
1005 }; | |
1006 template <> | 997 template <> |
1007 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pcmpeq::Emitter = { | 998 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pcmpeq::Emitter = { |
1008 &x86::AssemblerX86::pcmpeq, &x86::AssemblerX86::pcmpeq | 999 &x86::AssemblerX86::pcmpeq, &x86::AssemblerX86::pcmpeq}; |
1009 }; | |
1010 template <> | 1000 template <> |
1011 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pcmpgt::Emitter = { | 1001 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pcmpgt::Emitter = { |
1012 &x86::AssemblerX86::pcmpgt, &x86::AssemblerX86::pcmpgt | 1002 &x86::AssemblerX86::pcmpgt, &x86::AssemblerX86::pcmpgt}; |
1013 }; | |
1014 template <> | 1003 template <> |
1015 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pmull::Emitter = { | 1004 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pmull::Emitter = { |
1016 &x86::AssemblerX86::pmull, &x86::AssemblerX86::pmull | 1005 &x86::AssemblerX86::pmull, &x86::AssemblerX86::pmull}; |
1017 }; | |
1018 template <> | 1006 template <> |
1019 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pmuludq::Emitter = { | 1007 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pmuludq::Emitter = { |
1020 &x86::AssemblerX86::pmuludq, &x86::AssemblerX86::pmuludq | 1008 &x86::AssemblerX86::pmuludq, &x86::AssemblerX86::pmuludq}; |
1021 }; | |
1022 template <> | 1009 template <> |
1023 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Por::Emitter = { | 1010 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Por::Emitter = { |
1024 &x86::AssemblerX86::por, &x86::AssemblerX86::por | 1011 &x86::AssemblerX86::por, &x86::AssemblerX86::por}; |
1025 }; | |
1026 template <> | 1012 template <> |
1027 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Psub::Emitter = { | 1013 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Psub::Emitter = { |
1028 &x86::AssemblerX86::psub, &x86::AssemblerX86::psub | 1014 &x86::AssemblerX86::psub, &x86::AssemblerX86::psub}; |
1029 }; | |
1030 template <> | 1015 template <> |
1031 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pxor::Emitter = { | 1016 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pxor::Emitter = { |
1032 &x86::AssemblerX86::pxor, &x86::AssemblerX86::pxor | 1017 &x86::AssemblerX86::pxor, &x86::AssemblerX86::pxor}; |
1033 }; | |
1034 template <> | 1018 template <> |
1035 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Subss::Emitter = { | 1019 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Subss::Emitter = { |
1036 &x86::AssemblerX86::subss, &x86::AssemblerX86::subss | 1020 &x86::AssemblerX86::subss, &x86::AssemblerX86::subss}; |
1037 }; | |
1038 template <> | 1021 template <> |
1039 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Subps::Emitter = { | 1022 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Subps::Emitter = { |
1040 &x86::AssemblerX86::subps, &x86::AssemblerX86::subps | 1023 &x86::AssemblerX86::subps, &x86::AssemblerX86::subps}; |
1041 }; | |
1042 | 1024 |
1043 // Binary XMM Shift ops | 1025 // Binary XMM Shift ops |
1044 template <> | 1026 template <> |
1045 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psll::Emitter = { | 1027 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psll::Emitter = { |
1046 &x86::AssemblerX86::psll, &x86::AssemblerX86::psll, | 1028 &x86::AssemblerX86::psll, &x86::AssemblerX86::psll, |
1047 &x86::AssemblerX86::psll}; | 1029 &x86::AssemblerX86::psll}; |
1048 template <> | 1030 template <> |
1049 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psra::Emitter = { | 1031 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psra::Emitter = { |
1050 &x86::AssemblerX86::psra, &x86::AssemblerX86::psra, | 1032 &x86::AssemblerX86::psra, &x86::AssemblerX86::psra, |
1051 &x86::AssemblerX86::psra}; | 1033 &x86::AssemblerX86::psra}; |
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1749 Str << ", "; | 1731 Str << ", "; |
1750 getSrc(0)->emit(Func); | 1732 getSrc(0)->emit(Func); |
1751 } | 1733 } |
1752 | 1734 |
1753 void InstX8632Icmp::emitIAS(const Cfg *Func) const { | 1735 void InstX8632Icmp::emitIAS(const Cfg *Func) const { |
1754 assert(getSrcSize() == 2); | 1736 assert(getSrcSize() == 2); |
1755 const Operand *Src0 = getSrc(0); | 1737 const Operand *Src0 = getSrc(0); |
1756 const Operand *Src1 = getSrc(1); | 1738 const Operand *Src1 = getSrc(1); |
1757 Type Ty = Src0->getType(); | 1739 Type Ty = Src0->getType(); |
1758 static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = { | 1740 static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = { |
1759 &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp | 1741 &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp, |
1760 }; | 1742 &x86::AssemblerX86::cmp}; |
1761 static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = { | 1743 static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = { |
1762 &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp | 1744 &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp}; |
1763 }; | |
1764 if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) { | 1745 if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) { |
1765 if (SrcVar0->hasReg()) { | 1746 if (SrcVar0->hasReg()) { |
1766 emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter); | 1747 emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter); |
1767 return; | 1748 return; |
1768 } | 1749 } |
1769 } | 1750 } |
1770 emitIASAsAddrOpTyGPR(Func, Ty, Src0, Src1, AddrEmitter); | 1751 emitIASAsAddrOpTyGPR(Func, Ty, Src0, Src1, AddrEmitter); |
1771 } | 1752 } |
1772 | 1753 |
1773 void InstX8632Icmp::dump(const Cfg *Func) const { | 1754 void InstX8632Icmp::dump(const Cfg *Func) const { |
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1791 } | 1772 } |
1792 | 1773 |
1793 void InstX8632Ucomiss::emitIAS(const Cfg *Func) const { | 1774 void InstX8632Ucomiss::emitIAS(const Cfg *Func) const { |
1794 assert(getSrcSize() == 2); | 1775 assert(getSrcSize() == 2); |
1795 // Currently src0 is always a variable by convention, to avoid having | 1776 // Currently src0 is always a variable by convention, to avoid having |
1796 // two memory operands. | 1777 // two memory operands. |
1797 assert(llvm::isa<Variable>(getSrc(0))); | 1778 assert(llvm::isa<Variable>(getSrc(0))); |
1798 const auto Src0Var = llvm::cast<Variable>(getSrc(0)); | 1779 const auto Src0Var = llvm::cast<Variable>(getSrc(0)); |
1799 Type Ty = Src0Var->getType(); | 1780 Type Ty = Src0Var->getType(); |
1800 const static x86::AssemblerX86::XmmEmitterRegOp Emitter = { | 1781 const static x86::AssemblerX86::XmmEmitterRegOp Emitter = { |
1801 &x86::AssemblerX86::ucomiss, &x86::AssemblerX86::ucomiss | 1782 &x86::AssemblerX86::ucomiss, &x86::AssemblerX86::ucomiss}; |
1802 }; | |
1803 emitIASRegOpTyXMM(Func, Ty, Src0Var, getSrc(1), Emitter); | 1783 emitIASRegOpTyXMM(Func, Ty, Src0Var, getSrc(1), Emitter); |
1804 } | 1784 } |
1805 | 1785 |
1806 void InstX8632Ucomiss::dump(const Cfg *Func) const { | 1786 void InstX8632Ucomiss::dump(const Cfg *Func) const { |
1807 if (!ALLOW_DUMP) | 1787 if (!ALLOW_DUMP) |
1808 return; | 1788 return; |
1809 Ostream &Str = Func->getContext()->getStrDump(); | 1789 Ostream &Str = Func->getContext()->getStrDump(); |
1810 Str << "ucomiss." << getSrc(0)->getType() << " "; | 1790 Str << "ucomiss." << getSrc(0)->getType() << " "; |
1811 dumpSources(Func); | 1791 dumpSources(Func); |
1812 } | 1792 } |
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1844 | 1824 |
1845 void InstX8632Test::emitIAS(const Cfg *Func) const { | 1825 void InstX8632Test::emitIAS(const Cfg *Func) const { |
1846 assert(getSrcSize() == 2); | 1826 assert(getSrcSize() == 2); |
1847 const Operand *Src0 = getSrc(0); | 1827 const Operand *Src0 = getSrc(0); |
1848 const Operand *Src1 = getSrc(1); | 1828 const Operand *Src1 = getSrc(1); |
1849 Type Ty = Src0->getType(); | 1829 Type Ty = Src0->getType(); |
1850 // The Reg/Addr form of test is not encodeable. | 1830 // The Reg/Addr form of test is not encodeable. |
1851 static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = { | 1831 static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = { |
1852 &x86::AssemblerX86::test, nullptr, &x86::AssemblerX86::test}; | 1832 &x86::AssemblerX86::test, nullptr, &x86::AssemblerX86::test}; |
1853 static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = { | 1833 static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = { |
1854 &x86::AssemblerX86::test, &x86::AssemblerX86::test | 1834 &x86::AssemblerX86::test, &x86::AssemblerX86::test}; |
1855 }; | |
1856 if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) { | 1835 if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) { |
1857 if (SrcVar0->hasReg()) { | 1836 if (SrcVar0->hasReg()) { |
1858 emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter); | 1837 emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter); |
1859 return; | 1838 return; |
1860 } | 1839 } |
1861 } | 1840 } |
1862 llvm_unreachable("Nothing actually generates this so it's untested"); | 1841 llvm_unreachable("Nothing actually generates this so it's untested"); |
1863 emitIASAsAddrOpTyGPR(Func, Ty, Src0, Src1, AddrEmitter); | 1842 emitIASAsAddrOpTyGPR(Func, Ty, Src0, Src1, AddrEmitter); |
1864 } | 1843 } |
1865 | 1844 |
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2174 Str << ", "; | 2153 Str << ", "; |
2175 getDest()->emit(Func); | 2154 getDest()->emit(Func); |
2176 } | 2155 } |
2177 | 2156 |
2178 template <> void InstX8632Movp::emitIAS(const Cfg *Func) const { | 2157 template <> void InstX8632Movp::emitIAS(const Cfg *Func) const { |
2179 assert(getSrcSize() == 1); | 2158 assert(getSrcSize() == 1); |
2180 assert(isVectorType(getDest()->getType())); | 2159 assert(isVectorType(getDest()->getType())); |
2181 const Variable *Dest = getDest(); | 2160 const Variable *Dest = getDest(); |
2182 const Operand *Src = getSrc(0); | 2161 const Operand *Src = getSrc(0); |
2183 const static x86::AssemblerX86::XmmEmitterMovOps Emitter = { | 2162 const static x86::AssemblerX86::XmmEmitterMovOps Emitter = { |
2184 &x86::AssemblerX86::movups, &x86::AssemblerX86::movups, | 2163 &x86::AssemblerX86::movups, &x86::AssemblerX86::movups, |
2185 &x86::AssemblerX86::movups | 2164 &x86::AssemblerX86::movups}; |
2186 }; | |
2187 emitIASMovlikeXMM(Func, Dest, Src, Emitter); | 2165 emitIASMovlikeXMM(Func, Dest, Src, Emitter); |
2188 } | 2166 } |
2189 | 2167 |
2190 template <> void InstX8632Movq::emit(const Cfg *Func) const { | 2168 template <> void InstX8632Movq::emit(const Cfg *Func) const { |
2191 if (!ALLOW_DUMP) | 2169 if (!ALLOW_DUMP) |
2192 return; | 2170 return; |
2193 Ostream &Str = Func->getContext()->getStrEmit(); | 2171 Ostream &Str = Func->getContext()->getStrEmit(); |
2194 assert(getSrcSize() == 1); | 2172 assert(getSrcSize() == 1); |
2195 assert(getDest()->getType() == IceType_i64 || | 2173 assert(getDest()->getType() == IceType_i64 || |
2196 getDest()->getType() == IceType_f64); | 2174 getDest()->getType() == IceType_f64); |
2197 Str << "\tmovq\t"; | 2175 Str << "\tmovq\t"; |
2198 getSrc(0)->emit(Func); | 2176 getSrc(0)->emit(Func); |
2199 Str << ", "; | 2177 Str << ", "; |
2200 getDest()->emit(Func); | 2178 getDest()->emit(Func); |
2201 } | 2179 } |
2202 | 2180 |
2203 template <> void InstX8632Movq::emitIAS(const Cfg *Func) const { | 2181 template <> void InstX8632Movq::emitIAS(const Cfg *Func) const { |
2204 assert(getSrcSize() == 1); | 2182 assert(getSrcSize() == 1); |
2205 assert(getDest()->getType() == IceType_i64 || | 2183 assert(getDest()->getType() == IceType_i64 || |
2206 getDest()->getType() == IceType_f64); | 2184 getDest()->getType() == IceType_f64); |
2207 const Variable *Dest = getDest(); | 2185 const Variable *Dest = getDest(); |
2208 const Operand *Src = getSrc(0); | 2186 const Operand *Src = getSrc(0); |
2209 const static x86::AssemblerX86::XmmEmitterMovOps Emitter = { | 2187 const static x86::AssemblerX86::XmmEmitterMovOps Emitter = { |
2210 &x86::AssemblerX86::movq, &x86::AssemblerX86::movq, &x86::AssemblerX86::movq | 2188 &x86::AssemblerX86::movq, &x86::AssemblerX86::movq, |
2211 }; | 2189 &x86::AssemblerX86::movq}; |
2212 emitIASMovlikeXMM(Func, Dest, Src, Emitter); | 2190 emitIASMovlikeXMM(Func, Dest, Src, Emitter); |
2213 } | 2191 } |
2214 | 2192 |
2215 template <> void InstX8632MovssRegs::emitIAS(const Cfg *Func) const { | 2193 template <> void InstX8632MovssRegs::emitIAS(const Cfg *Func) const { |
2216 // This is Binop variant is only intended to be used for reg-reg moves | 2194 // This is Binop variant is only intended to be used for reg-reg moves |
2217 // where part of the Dest register is untouched. | 2195 // where part of the Dest register is untouched. |
2218 assert(getSrcSize() == 2); | 2196 assert(getSrcSize() == 2); |
2219 const Variable *Dest = getDest(); | 2197 const Variable *Dest = getDest(); |
2220 assert(Dest == getSrc(0)); | 2198 assert(Dest == getSrc(0)); |
2221 const auto SrcVar = llvm::cast<Variable>(getSrc(1)); | 2199 const auto SrcVar = llvm::cast<Variable>(getSrc(1)); |
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2425 } | 2403 } |
2426 | 2404 |
2427 template <> void InstX8632Pextr::emit(const Cfg *Func) const { | 2405 template <> void InstX8632Pextr::emit(const Cfg *Func) const { |
2428 if (!ALLOW_DUMP) | 2406 if (!ALLOW_DUMP) |
2429 return; | 2407 return; |
2430 Ostream &Str = Func->getContext()->getStrEmit(); | 2408 Ostream &Str = Func->getContext()->getStrEmit(); |
2431 assert(getSrcSize() == 2); | 2409 assert(getSrcSize() == 2); |
2432 // pextrb and pextrd are SSE4.1 instructions. | 2410 // pextrb and pextrd are SSE4.1 instructions. |
2433 assert(getSrc(0)->getType() == IceType_v8i16 || | 2411 assert(getSrc(0)->getType() == IceType_v8i16 || |
2434 getSrc(0)->getType() == IceType_v8i1 || | 2412 getSrc(0)->getType() == IceType_v8i1 || |
2435 static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() | 2413 static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >= |
2436 >= TargetX8632::SSE4_1); | 2414 TargetX8632::SSE4_1); |
2437 Str << "\t" << Opcode | 2415 Str << "\t" << Opcode << TypeX8632Attributes[getSrc(0)->getType()].PackString |
2438 << TypeX8632Attributes[getSrc(0)->getType()].PackString << "\t"; | 2416 << "\t"; |
2439 getSrc(1)->emit(Func); | 2417 getSrc(1)->emit(Func); |
2440 Str << ", "; | 2418 Str << ", "; |
2441 getSrc(0)->emit(Func); | 2419 getSrc(0)->emit(Func); |
2442 Str << ", "; | 2420 Str << ", "; |
2443 Variable *Dest = getDest(); | 2421 Variable *Dest = getDest(); |
2444 // pextrw must take a register dest. There is an SSE4.1 version that takes | 2422 // pextrw must take a register dest. There is an SSE4.1 version that takes |
2445 // a memory dest, but we aren't using it. For uniformity, just restrict | 2423 // a memory dest, but we aren't using it. For uniformity, just restrict |
2446 // them all to have a register dest for now. | 2424 // them all to have a register dest for now. |
2447 assert(Dest->hasReg()); | 2425 assert(Dest->hasReg()); |
2448 Dest->asType(IceType_i32)->emit(Func); | 2426 Dest->asType(IceType_i32)->emit(Func); |
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2471 } | 2449 } |
2472 | 2450 |
2473 template <> void InstX8632Pinsr::emit(const Cfg *Func) const { | 2451 template <> void InstX8632Pinsr::emit(const Cfg *Func) const { |
2474 if (!ALLOW_DUMP) | 2452 if (!ALLOW_DUMP) |
2475 return; | 2453 return; |
2476 Ostream &Str = Func->getContext()->getStrEmit(); | 2454 Ostream &Str = Func->getContext()->getStrEmit(); |
2477 assert(getSrcSize() == 3); | 2455 assert(getSrcSize() == 3); |
2478 // pinsrb and pinsrd are SSE4.1 instructions. | 2456 // pinsrb and pinsrd are SSE4.1 instructions. |
2479 assert(getDest()->getType() == IceType_v8i16 || | 2457 assert(getDest()->getType() == IceType_v8i16 || |
2480 getDest()->getType() == IceType_v8i1 || | 2458 getDest()->getType() == IceType_v8i1 || |
2481 static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() | 2459 static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >= |
2482 >= TargetX8632::SSE4_1); | 2460 TargetX8632::SSE4_1); |
2483 Str << "\t" << Opcode | 2461 Str << "\t" << Opcode << TypeX8632Attributes[getDest()->getType()].PackString |
2484 << TypeX8632Attributes[getDest()->getType()].PackString << "\t"; | 2462 << "\t"; |
2485 getSrc(2)->emit(Func); | 2463 getSrc(2)->emit(Func); |
2486 Str << ", "; | 2464 Str << ", "; |
2487 Operand *Src1 = getSrc(1); | 2465 Operand *Src1 = getSrc(1); |
2488 if (const auto Src1Var = llvm::dyn_cast<Variable>(Src1)) { | 2466 if (const auto Src1Var = llvm::dyn_cast<Variable>(Src1)) { |
2489 // If src1 is a register, it should always be r32. | 2467 // If src1 is a register, it should always be r32. |
2490 if (Src1Var->hasReg()) { | 2468 if (Src1Var->hasReg()) { |
2491 Src1Var->asType(IceType_i32)->emit(Func); | 2469 Src1Var->asType(IceType_i32)->emit(Func); |
2492 } else { | 2470 } else { |
2493 Src1Var->emit(Func); | 2471 Src1Var->emit(Func); |
2494 } | 2472 } |
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2909 } | 2887 } |
2910 Str << "("; | 2888 Str << "("; |
2911 if (Func) | 2889 if (Func) |
2912 Var->dump(Func); | 2890 Var->dump(Func); |
2913 else | 2891 else |
2914 Var->dump(Str); | 2892 Var->dump(Str); |
2915 Str << ")"; | 2893 Str << ")"; |
2916 } | 2894 } |
2917 | 2895 |
2918 } // end of namespace Ice | 2896 } // end of namespace Ice |
OLD | NEW |