Subzero: Use a "known" version of clang-format.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 16 matching lines @@
 namespace {
 
 const struct InstX8632BrAttributes_ {
   CondX86::BrCond Opposite;
   const char *DisplayString;
   const char *EmitString;
 } InstX8632BrAttributes[] = {
 #define X(tag, encode, opp, dump, emit)                                        \
   { CondX86::opp, dump, emit }                                                 \
   ,
-    ICEINSTX8632BR_TABLE
+      ICEINSTX8632BR_TABLE
 #undef X
-  };
+};
 
 const struct InstX8632CmppsAttributes_ {
   const char *EmitString;
 } InstX8632CmppsAttributes[] = {
 #define X(tag, emit)                                                           \
   { emit }                                                                     \
   ,
-    ICEINSTX8632CMPPS_TABLE
+      ICEINSTX8632CMPPS_TABLE
 #undef X
-  };
+};
 
 const struct TypeX8632Attributes_ {
   const char *CvtString;   // i (integer), s (single FP), d (double FP)
   const char *SdSsString;  // ss, sd, or <blank>
   const char *PackString;  // b, w, d, or <blank>
   const char *WidthString; // b, w, l, q, or <blank>
   const char *FldString;   // s, l, or <blank>
 } TypeX8632Attributes[] = {
 #define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
   { cvt, sdss, pack, width, fld }                                              \
   ,
-    ICETYPEX8632_TABLE
+      ICETYPEX8632_TABLE
 #undef X
-  };
+};
 
 const char *InstX8632SegmentRegNames[] = {
 #define X(val, name, prefix) name,
     SEG_REGX8632_TABLE
 #undef X
 };
 
 uint8_t InstX8632SegmentPrefixes[] = {
 #define X(val, name, prefix) prefix,
     SEG_REGX8632_TABLE
@@ skipping 819 matching lines @@
 template <> const char *InstX8632Pinsr::Opcode = "pinsr";
 template <> const char *InstX8632Blendvps::Opcode = "blendvps";
 template <> const char *InstX8632Pblendvb::Opcode = "pblendvb";
 // Three address ops
 template <> const char *InstX8632Pextr::Opcode = "pextr";
 template <> const char *InstX8632Pshufd::Opcode = "pshufd";
 
 // Inplace GPR ops
 template <>
 const x86::AssemblerX86::GPREmitterOneOp InstX8632Bswap::Emitter = {
-    &x86::AssemblerX86::bswap, nullptr /* only a reg form exists */};
+    &x86::AssemblerX86::bswap, nullptr /* only a reg form exists */
+};
 template <>
 const x86::AssemblerX86::GPREmitterOneOp InstX8632Neg::Emitter = {
     &x86::AssemblerX86::neg, &x86::AssemblerX86::neg};
 
 // Unary GPR ops
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Bsf::Emitter = {
     &x86::AssemblerX86::bsf, &x86::AssemblerX86::bsf, nullptr};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Bsr::Emitter = {
     &x86::AssemblerX86::bsr, &x86::AssemblerX86::bsr, nullptr};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Lea::Emitter = {
     /* reg/reg and reg/imm are illegal */ nullptr, &x86::AssemblerX86::lea,
     nullptr};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Movsx::Emitter = {
     &x86::AssemblerX86::movsx, &x86::AssemblerX86::movsx, nullptr};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Movzx::Emitter = {
     &x86::AssemblerX86::movzx, &x86::AssemblerX86::movzx, nullptr};
 
 // Unary XMM ops
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Sqrtss::Emitter = {
-  &x86::AssemblerX86::sqrtss, &x86::AssemblerX86::sqrtss
-};
+    &x86::AssemblerX86::sqrtss, &x86::AssemblerX86::sqrtss};
 
 // Binary GPR ops
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Add::Emitter = {
     &x86::AssemblerX86::add, &x86::AssemblerX86::add, &x86::AssemblerX86::add};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Adc::Emitter = {
     &x86::AssemblerX86::adc, &x86::AssemblerX86::adc, &x86::AssemblerX86::adc};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632And::Emitter = {
@@ skipping 21 matching lines @@
 template <>
 const x86::AssemblerX86::GPREmitterShiftOp InstX8632Shl::Emitter = {
     &x86::AssemblerX86::shl, &x86::AssemblerX86::shl};
 template <>
 const x86::AssemblerX86::GPREmitterShiftOp InstX8632Shr::Emitter = {
     &x86::AssemblerX86::shr, &x86::AssemblerX86::shr};
 
 // Binary XMM ops
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Addss::Emitter = {
-  &x86::AssemblerX86::addss, &x86::AssemblerX86::addss
-};
+    &x86::AssemblerX86::addss, &x86::AssemblerX86::addss};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Addps::Emitter = {
-  &x86::AssemblerX86::addps, &x86::AssemblerX86::addps
-};
+    &x86::AssemblerX86::addps, &x86::AssemblerX86::addps};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Divss::Emitter = {
-  &x86::AssemblerX86::divss, &x86::AssemblerX86::divss
-};
+    &x86::AssemblerX86::divss, &x86::AssemblerX86::divss};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Divps::Emitter = {
-  &x86::AssemblerX86::divps, &x86::AssemblerX86::divps
-};
+    &x86::AssemblerX86::divps, &x86::AssemblerX86::divps};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Mulss::Emitter = {
-  &x86::AssemblerX86::mulss, &x86::AssemblerX86::mulss
-};
+    &x86::AssemblerX86::mulss, &x86::AssemblerX86::mulss};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Mulps::Emitter = {
-  &x86::AssemblerX86::mulps, &x86::AssemblerX86::mulps
-};
+    &x86::AssemblerX86::mulps, &x86::AssemblerX86::mulps};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Padd::Emitter = {
-  &x86::AssemblerX86::padd, &x86::AssemblerX86::padd
-};
+    &x86::AssemblerX86::padd, &x86::AssemblerX86::padd};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pand::Emitter = {
-  &x86::AssemblerX86::pand, &x86::AssemblerX86::pand
-};
+    &x86::AssemblerX86::pand, &x86::AssemblerX86::pand};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pandn::Emitter = {
-  &x86::AssemblerX86::pandn, &x86::AssemblerX86::pandn
-};
+    &x86::AssemblerX86::pandn, &x86::AssemblerX86::pandn};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pcmpeq::Emitter = {
-  &x86::AssemblerX86::pcmpeq, &x86::AssemblerX86::pcmpeq
-};
+    &x86::AssemblerX86::pcmpeq, &x86::AssemblerX86::pcmpeq};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pcmpgt::Emitter = {
-  &x86::AssemblerX86::pcmpgt, &x86::AssemblerX86::pcmpgt
-};
+    &x86::AssemblerX86::pcmpgt, &x86::AssemblerX86::pcmpgt};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pmull::Emitter = {
-  &x86::AssemblerX86::pmull, &x86::AssemblerX86::pmull
-};
+    &x86::AssemblerX86::pmull, &x86::AssemblerX86::pmull};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pmuludq::Emitter = {
-  &x86::AssemblerX86::pmuludq, &x86::AssemblerX86::pmuludq
-};
+    &x86::AssemblerX86::pmuludq, &x86::AssemblerX86::pmuludq};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Por::Emitter = {
-  &x86::AssemblerX86::por, &x86::AssemblerX86::por
-};
+    &x86::AssemblerX86::por, &x86::AssemblerX86::por};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Psub::Emitter = {
-  &x86::AssemblerX86::psub, &x86::AssemblerX86::psub
-};
+    &x86::AssemblerX86::psub, &x86::AssemblerX86::psub};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pxor::Emitter = {
-  &x86::AssemblerX86::pxor, &x86::AssemblerX86::pxor
-};
+    &x86::AssemblerX86::pxor, &x86::AssemblerX86::pxor};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Subss::Emitter = {
-  &x86::AssemblerX86::subss, &x86::AssemblerX86::subss
-};
+    &x86::AssemblerX86::subss, &x86::AssemblerX86::subss};
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Subps::Emitter = {
-  &x86::AssemblerX86::subps, &x86::AssemblerX86::subps
-};
+    &x86::AssemblerX86::subps, &x86::AssemblerX86::subps};
 
 // Binary XMM Shift ops
 template <>
 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psll::Emitter = {
     &x86::AssemblerX86::psll, &x86::AssemblerX86::psll,
     &x86::AssemblerX86::psll};
 template <>
 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psra::Emitter = {
     &x86::AssemblerX86::psra, &x86::AssemblerX86::psra,
     &x86::AssemblerX86::psra};
@@ skipping 697 matching lines @@
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 void InstX8632Icmp::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Operand *Src0 = getSrc(0);
   const Operand *Src1 = getSrc(1);
   Type Ty = Src0->getType();
   static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = {
-    &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp
-  };
+      &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp,
+      &x86::AssemblerX86::cmp};
   static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = {
-    &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp
-  };
+      &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp};
   if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar0->hasReg()) {
       emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
       return;
     }
   }
   emitIASAsAddrOpTyGPR(Func, Ty, Src0, Src1, AddrEmitter);
 }
 
 void InstX8632Icmp::dump(const Cfg *Func) const {
@@ skipping 17 matching lines @@
 }
 
 void InstX8632Ucomiss::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   // Currently src0 is always a variable by convention, to avoid having
   // two memory operands.
   assert(llvm::isa<Variable>(getSrc(0)));
   const auto Src0Var = llvm::cast<Variable>(getSrc(0));
   Type Ty = Src0Var->getType();
   const static x86::AssemblerX86::XmmEmitterRegOp Emitter = {
-    &x86::AssemblerX86::ucomiss, &x86::AssemblerX86::ucomiss
-  };
+      &x86::AssemblerX86::ucomiss, &x86::AssemblerX86::ucomiss};
   emitIASRegOpTyXMM(Func, Ty, Src0Var, getSrc(1), Emitter);
 }
 
 void InstX8632Ucomiss::dump(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "ucomiss." << getSrc(0)->getType() << " ";
   dumpSources(Func);
 }
@@ skipping 31 matching lines @@
 
 void InstX8632Test::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Operand *Src0 = getSrc(0);
   const Operand *Src1 = getSrc(1);
   Type Ty = Src0->getType();
   // The Reg/Addr form of test is not encodeable.
   static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = {
       &x86::AssemblerX86::test, nullptr, &x86::AssemblerX86::test};
   static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = {
-    &x86::AssemblerX86::test, &x86::AssemblerX86::test
-  };
+      &x86::AssemblerX86::test, &x86::AssemblerX86::test};
   if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar0->hasReg()) {
       emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
       return;
     }
   }
   llvm_unreachable("Nothing actually generates this so it's untested");
   emitIASAsAddrOpTyGPR(Func, Ty, Src0, Src1, AddrEmitter);
 }
 
@@ skipping 308 matching lines @@
   Str << ", ";
   getDest()->emit(Func);
 }
 
 template <> void InstX8632Movp::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   assert(isVectorType(getDest()->getType()));
   const Variable *Dest = getDest();
   const Operand *Src = getSrc(0);
   const static x86::AssemblerX86::XmmEmitterMovOps Emitter = {
-    &x86::AssemblerX86::movups, &x86::AssemblerX86::movups,
-    &x86::AssemblerX86::movups
-  };
+      &x86::AssemblerX86::movups, &x86::AssemblerX86::movups,
+      &x86::AssemblerX86::movups};
   emitIASMovlikeXMM(Func, Dest, Src, Emitter);
 }
 
 template <> void InstX8632Movq::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->getType() == IceType_i64 ||
          getDest()->getType() == IceType_f64);
   Str << "\tmovq\t";
   getSrc(0)->emit(Func);
   Str << ", ";
   getDest()->emit(Func);
 }
 
 template <> void InstX8632Movq::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   assert(getDest()->getType() == IceType_i64 ||
          getDest()->getType() == IceType_f64);
   const Variable *Dest = getDest();
   const Operand *Src = getSrc(0);
   const static x86::AssemblerX86::XmmEmitterMovOps Emitter = {
-    &x86::AssemblerX86::movq, &x86::AssemblerX86::movq, &x86::AssemblerX86::movq
-  };
+      &x86::AssemblerX86::movq, &x86::AssemblerX86::movq,
+      &x86::AssemblerX86::movq};
   emitIASMovlikeXMM(Func, Dest, Src, Emitter);
 }
 
 template <> void InstX8632MovssRegs::emitIAS(const Cfg *Func) const {
   // This is Binop variant is only intended to be used for reg-reg moves
   // where part of the Dest register is untouched.
   assert(getSrcSize() == 2);
   const Variable *Dest = getDest();
   assert(Dest == getSrc(0));
   const auto SrcVar = llvm::cast<Variable>(getSrc(1));
@@ skipping 203 matching lines @@
 }
 
 template <> void InstX8632Pextr::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   assert(getSrc(0)->getType() == IceType_v8i16 ||
          getSrc(0)->getType() == IceType_v8i1 ||
-         static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
-             >= TargetX8632::SSE4_1);
-  Str << "\t" << Opcode
-      << TypeX8632Attributes[getSrc(0)->getType()].PackString << "\t";
+         static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
+             TargetX8632::SSE4_1);
+  Str << "\t" << Opcode << TypeX8632Attributes[getSrc(0)->getType()].PackString
+      << "\t";
   getSrc(1)->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
   Str << ", ";
   Variable *Dest = getDest();
   // pextrw must take a register dest. There is an SSE4.1 version that takes
   // a memory dest, but we aren't using it. For uniformity, just restrict
   // them all to have a register dest for now.
   assert(Dest->hasReg());
   Dest->asType(IceType_i32)->emit(Func);
@@ skipping 22 matching lines @@
 }
 
 template <> void InstX8632Pinsr::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
   // pinsrb and pinsrd are SSE4.1 instructions.
   assert(getDest()->getType() == IceType_v8i16 ||
          getDest()->getType() == IceType_v8i1 ||
-         static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
-             >= TargetX8632::SSE4_1);
-  Str << "\t" << Opcode
-      << TypeX8632Attributes[getDest()->getType()].PackString << "\t";
+         static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
+             TargetX8632::SSE4_1);
+  Str << "\t" << Opcode << TypeX8632Attributes[getDest()->getType()].PackString
+      << "\t";
   getSrc(2)->emit(Func);
   Str << ", ";
   Operand *Src1 = getSrc(1);
   if (const auto Src1Var = llvm::dyn_cast<Variable>(Src1)) {
     // If src1 is a register, it should always be r32.
     if (Src1Var->hasReg()) {
       Src1Var->asType(IceType_i32)->emit(Func);
     } else {
       Src1Var->emit(Func);
     }
@@ skipping 414 matching lines @@
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // end of namespace Ice