Subzero: Initial implementation of multithreaded translation.

src/IceRegAlloc.cpp

 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the LinearScan class, which performs the
@@ skipping 34 matching lines @@
     if (Item->getLiveRange().overlapsInst(Defs[i]->getNumber(), UseTrimmed))
       return true;
   }
   return false;
 }
 
 void dumpDisableOverlap(const Cfg *Func, const Variable *Var,
                         const char *Reason) {
   if (!ALLOW_DUMP)
     return;
-  if (Func->getContext()->isVerbose(IceV_LinearScan)) {
+  if (Func->isVerbose(IceV_LinearScan)) {
     VariablesMetadata *VMetadata = Func->getVMetadata();
     Ostream &Str = Func->getContext()->getStrDump();
     Str << "Disabling Overlap due to " << Reason << " " << *Var
         << " LIVE=" << Var->getLiveRange() << " Defs=";
     if (const Inst *FirstDef = VMetadata->getFirstDefinition(Var))
       Str << FirstDef->getNumber();
     const InstDefList &Defs = VMetadata->getLatterDefinitions(Var);
     for (size_t i = 0; i < Defs.size(); ++i) {
       Str << "," << Defs[i]->getNumber();
     }
@@ skipping 192 matching lines @@
 // cases.
 //
 // Requires running Cfg::liveness(Liveness_Intervals) in
 // preparation.  Results are assigned to Variable::RegNum for each
 // Variable.
 void LinearScan::scan(const llvm::SmallBitVector &RegMaskFull,
                       bool Randomized) {
   TimerMarker T(TimerStack::TT_linearScan, Func);
   assert(RegMaskFull.any()); // Sanity check
   GlobalContext *Ctx = Func->getContext();
-  const bool Verbose =
-      ALLOW_DUMP && Ctx->isVerbose(IceV_LinearScan);
+  const bool Verbose = ALLOW_DUMP && Func->isVerbose(IceV_LinearScan);
   if (Verbose)
     Ctx->lockStr();
   Func->resetCurrentNode();
   VariablesMetadata *VMetadata = Func->getVMetadata();
   const size_t NumRegisters = RegMaskFull.size();
   llvm::SmallBitVector PreDefinedRegisters(NumRegisters);
   if (Randomized) {
     for (Variable *Var : UnhandledPrecolored) {
       PreDefinedRegisters[Var->getRegNum()] = true;
     }
@@ skipping 451 matching lines @@
 
   if (Verbose)
     Ctx->unlockStr();
 }
 
 // ======================== Dump routines ======================== //
 
 void LinearScan::dump(Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
-  if (!Func->getContext()->isVerbose(IceV_LinearScan))
+  if (!Func->isVerbose(IceV_LinearScan))
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Func->resetCurrentNode();
   Str << "**** Current regalloc state:\n";
   Str << "++++++ Handled:\n";
   for (const Variable *Item : Handled) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Unhandled:\n";
   for (const Variable *Item : reverse_range(Unhandled)) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Active:\n";
   for (const Variable *Item : Active) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Inactive:\n";
   for (const Variable *Item : Inactive) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
 }
 
 } // end of namespace Ice