OLD | NEW |
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
(...skipping 2816 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2827 UNREACHABLE(); | 2827 UNREACHABLE(); |
2828 return (Address)0x0; | 2828 return (Address)0x0; |
2829 } | 2829 } |
2830 | 2830 |
2831 | 2831 |
2832 // MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32 | 2832 // MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32 |
2833 // qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap | 2833 // qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap |
2834 // snapshot generated on ia32, the resulting MIPS sNaN must be quieted. | 2834 // snapshot generated on ia32, the resulting MIPS sNaN must be quieted. |
2835 // OS::nan_value() returns a qNaN. | 2835 // OS::nan_value() returns a qNaN. |
2836 void Assembler::QuietNaN(HeapObject* object) { | 2836 void Assembler::QuietNaN(HeapObject* object) { |
2837 HeapNumber::cast(object)->set_value(base::OS::nan_value()); | 2837 HeapNumber::cast(object)->set_value(std::numeric_limits<double>::quiet_NaN()); |
2838 } | 2838 } |
2839 | 2839 |
2840 | 2840 |
2841 // On Mips64, a target address is stored in a 4-instruction sequence: | 2841 // On Mips64, a target address is stored in a 4-instruction sequence: |
2842 // 0: lui(rd, (j.imm64_ >> 32) & kImm16Mask); | 2842 // 0: lui(rd, (j.imm64_ >> 32) & kImm16Mask); |
2843 // 1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask); | 2843 // 1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask); |
2844 // 2: dsll(rd, rd, 16); | 2844 // 2: dsll(rd, rd, 16); |
2845 // 3: ori(rd, rd, j.imm32_ & kImm16Mask); | 2845 // 3: ori(rd, rd, j.imm32_ & kImm16Mask); |
2846 // | 2846 // |
2847 // Patching the address must replace all the lui & ori instructions, | 2847 // Patching the address must replace all the lui & ori instructions, |
(...skipping 84 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2932 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { | 2932 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { |
2933 // No out-of-line constant pool support. | 2933 // No out-of-line constant pool support. |
2934 DCHECK(!FLAG_enable_ool_constant_pool); | 2934 DCHECK(!FLAG_enable_ool_constant_pool); |
2935 return; | 2935 return; |
2936 } | 2936 } |
2937 | 2937 |
2938 | 2938 |
2939 } } // namespace v8::internal | 2939 } } // namespace v8::internal |
2940 | 2940 |
2941 #endif // V8_TARGET_ARCH_MIPS64 | 2941 #endif // V8_TARGET_ARCH_MIPS64 |
OLD | NEW |