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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2568 UNREACHABLE(); | 2568 UNREACHABLE(); |
2569 return (Address)0x0; | 2569 return (Address)0x0; |
2570 } | 2570 } |
2571 | 2571 |
2572 | 2572 |
2573 // MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32 | 2573 // MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32 |
2574 // qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap | 2574 // qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap |
2575 // snapshot generated on ia32, the resulting MIPS sNaN must be quieted. | 2575 // snapshot generated on ia32, the resulting MIPS sNaN must be quieted. |
2576 // OS::nan_value() returns a qNaN. | 2576 // OS::nan_value() returns a qNaN. |
2577 void Assembler::QuietNaN(HeapObject* object) { | 2577 void Assembler::QuietNaN(HeapObject* object) { |
2578 HeapNumber::cast(object)->set_value(base::OS::nan_value()); | 2578 HeapNumber::cast(object)->set_value(std::numeric_limits<double>::quiet_NaN()); |
2579 } | 2579 } |
2580 | 2580 |
2581 | 2581 |
2582 // On Mips, a target address is stored in a lui/ori instruction pair, each | 2582 // On Mips, a target address is stored in a lui/ori instruction pair, each |
2583 // of which load 16 bits of the 32-bit address to a register. | 2583 // of which load 16 bits of the 32-bit address to a register. |
2584 // Patching the address must replace both instr, and flush the i-cache. | 2584 // Patching the address must replace both instr, and flush the i-cache. |
2585 // | 2585 // |
2586 // There is an optimization below, which emits a nop when the address | 2586 // There is an optimization below, which emits a nop when the address |
2587 // fits in just 16 bits. This is unlikely to help, and should be benchmarked, | 2587 // fits in just 16 bits. This is unlikely to help, and should be benchmarked, |
2588 // and possibly removed. | 2588 // and possibly removed. |
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2740 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { | 2740 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { |
2741 // No out-of-line constant pool support. | 2741 // No out-of-line constant pool support. |
2742 DCHECK(!FLAG_enable_ool_constant_pool); | 2742 DCHECK(!FLAG_enable_ool_constant_pool); |
2743 return; | 2743 return; |
2744 } | 2744 } |
2745 | 2745 |
2746 | 2746 |
2747 } } // namespace v8::internal | 2747 } } // namespace v8::internal |
2748 | 2748 |
2749 #endif // V8_TARGET_ARCH_MIPS | 2749 #endif // V8_TARGET_ARCH_MIPS |
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