Update from https://crrev.com/312398

third_party/boringssl/linux-arm/crypto/sha/sha512-armv4.S

-#if defined(__arm__)
 #include "arm_arch.h"
 #ifdef __ARMEL__
 # define LO 0
 # define HI 4
 # define WORD64(hi0,lo0,hi1,lo1)        .word   lo0,hi0, lo1,hi1
 #else
 # define HI 0
 # define LO 4
 # define WORD64(hi0,lo0,hi1,lo1)        .word   hi0,lo0, hi1,lo1
 #endif
@@ skipping 37 matching lines @@
 WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b)
 WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207)
 WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178)
 WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6)
 WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b)
 WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493)
 WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c)
 WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
 WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
 .size   K512,.-K512
+#if __ARM_MAX_ARCH__>=7
 .LOPENSSL_armcap:
 .word   OPENSSL_armcap_P-sha512_block_data_order
 .skip   32-4
+#else
+.skip   32
+#endif
 
 .global sha512_block_data_order
-.hidden sha512_block_data_order
 .type   sha512_block_data_order,%function
 sha512_block_data_order:
         sub     r3,pc,#8                @ sha512_block_data_order
         add     r2,r1,r2,lsl#7  @ len to point at the end of inp
-#if __ARM_ARCH__>=7
+#if __ARM_MAX_ARCH__>=7
         ldr     r12,.LOPENSSL_armcap
         ldr     r12,[r3,r12]            @ OPENSSL_armcap_P
         tst     r12,#1
         bne     .LNEON
 #endif
         stmdb   sp!,{r4-r12,lr}
         sub     r14,r3,#672             @ K512
         sub     sp,sp,#9*8
 
         ldr     r7,[r0,#32+LO]
@@ skipping 352 matching lines @@
 
         add     sp,sp,#8*9              @ destroy frame
 #if __ARM_ARCH__>=5
         ldmia   sp!,{r4-r12,pc}
 #else
         ldmia   sp!,{r4-r12,lr}
         tst     lr,#1
         moveq   pc,lr                   @ be binary compatible with V4, yet
         .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
 #endif
-#if __ARM_ARCH__>=7
+#if __ARM_MAX_ARCH__>=7
+.arch   armv7-a
 .fpu    neon
 
 .align  4
 .LNEON:
         dmb                             @ errata #451034 on early Cortex A8
         vstmdb  sp!,{d8-d15}            @ ABI specification says so
         sub     r3,r3,#672              @ K512
         vldmia  r0,{d16-d23}            @ load context
 .Loop_neon:
         vshr.u64        d24,d20,#14     @ 0
@@ skipping 1302 matching lines @@
         vadd.i64        q8,q12          @ vectorized accumulate
         vadd.i64        q9,q13
         vadd.i64        q10,q14
         vadd.i64        q11,q15
         vstmia          r0,{d16-d23}    @ save context
         teq             r1,r2
         sub             r3,#640 @ rewind K512
         bne             .Loop_neon
 
         vldmia  sp!,{d8-d15}            @ epilogue
-        .word   0xe12fff1e
+        bx      lr                              @ .word 0xe12fff1e
 #endif
 .size   sha512_block_data_order,.-sha512_block_data_order
 .asciz  "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
 .align  2
+#if __ARM_MAX_ARCH__>=7
 .comm   OPENSSL_armcap_P,4,4
-
 #endif