test/Transforms/NaCl/atomic/lock_.ll - Issue 857403002: Emit atomic memory order other than seq_cst on demand only

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Side by Side Diff: test/Transforms/NaCl/atomic/lock_.ll

Issue 857403002: Emit atomic memory order other than seq_cst on demand only (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-llvm.git@master

Patch Set: Add test for -pnacl-memory-order-seq-cst-only=true Created 5 years, 11 months ago

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1 ; RUN: opt -nacl-rewrite-atomics -S < %s \| FileCheck %s	1 ; RUN: opt -nacl-rewrite-atomics -pnacl-memory-order-seq-cst-only=false -S < %s \| FileCheck %s

2	2

3 ; Each of these tests validates that the corresponding legacy GCC-style builtins	3 ; Each of these tests validates that the corresponding legacy GCC-style builtins

4 ; are properly rewritten to NaCl atomic builtins. Only the GCC-style builtins	4 ; are properly rewritten to NaCl atomic builtins. Only the GCC-style builtins

5 ; that have corresponding primitives in C11/C++11 and which emit different code	5 ; that have corresponding primitives in C11/C++11 and which emit different code

6 ; are tested. These legacy GCC-builtins only support sequential-consistency	6 ; are tested. These legacy GCC-builtins only support sequential-consistency

7 ; (enum value 6).	7 ; (enum value 6).

8 ;	8 ;

9 ; test_* tests the corresponding __sync_* builtin. See:	9 ; test_* tests the corresponding __sync_* builtin. See:

10 ; http://gcc.gnu.org/onlinedocs/gcc-4.8.1/gcc/_005f_005fsync-Builtins.html	10 ; http://gcc.gnu.org/onlinedocs/gcc-4.8.1/gcc/_005f_005fsync-Builtins.html

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59 %res = atomicrmw xchg i64* %ptr, i64 %value seq_cst	59 %res = atomicrmw xchg i64* %ptr, i64 %value seq_cst

60 ret i64 %res ; CHECK-NEXT: ret i64 %res	60 ret i64 %res ; CHECK-NEXT: ret i64 %res

61 }	61 }

62	62

63 ; CHECK-LABEL: @test_lock_release_i64	63 ; CHECK-LABEL: @test_lock_release_i64

64 define void @test_lock_release_i64(i64* %ptr) {	64 define void @test_lock_release_i64(i64* %ptr) {

65 ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 0, i64* %ptr, i32 4)	65 ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 0, i64* %ptr, i32 4)

66 store atomic i64 0, i64* %ptr release, align 8	66 store atomic i64 0, i64* %ptr release, align 8

67 ret void ; CHECK-NEXT: ret void	67 ret void ; CHECK-NEXT: ret void

68 }	68 }

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