Emit atomic memory order other than seq_cst on demand only

lib/Transforms/NaCl/RewriteAtomics.cpp

 //===- RewriteAtomics.cpp - Stabilize instructions used for concurrency ---===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This pass encodes atomics, volatiles and fences using NaCl intrinsics
 // instead of LLVM's regular IR instructions.
 //
 // All of the above are transformed into one of the
 // @llvm.nacl.atomic.* intrinsics.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/Twine.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/InlineAsm.h"
+#include "llvm/IR/InstVisitor.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/NaClAtomicIntrinsics.h"
-#include "llvm/IR/InstVisitor.h"
 #include "llvm/Pass.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/NaCl.h"
 #include <climits>
 #include <string>
 
 using namespace llvm;
 
+// TODO(jfb) Keep the default of this option to true for Chrome 42, and change
+//           it to false for Chrome 43. This allows the PNaCl translator to be
+//           updated before the SDK starts emitting atomic memory orders that
+//           the old translator rejected.
+static cl::opt<bool> PNaClMemoryOrderSeqCstOnly(
+    "pnacl-memory-order-seq-cst-only",
+    cl::desc("PNaCl should upgrade all atomic memory orders to seq_cst"),
+    cl::init(true));
+
 namespace {
+
 class RewriteAtomics : public ModulePass {
 public:
   static char ID; // Pass identification, replacement for typeid
   RewriteAtomics() : ModulePass(ID) {
     // This is a module pass because it may have to introduce
     // intrinsic declarations into the module and modify a global function.
     initializeRewriteAtomicsPass(*PassRegistry::getPassRegistry());
   }
 
   virtual bool runOnModule(Module &M);
@@ skipping 141 matching lines @@
     // TODO Consume is currently unspecified by LLVM's internal IR.
     case Acquire: AO = NaCl::MemoryOrderAcquire; break;
     case Release: AO = NaCl::MemoryOrderRelease; break;
     case AcquireRelease: AO = NaCl::MemoryOrderAcquireRelease; break;
     case SequentiallyConsistent:
       AO = NaCl::MemoryOrderSequentiallyConsistent; break;
     }
   }
 
   // TODO For now only acquire/release/acq_rel/seq_cst are allowed.
-  if (AO == NaCl::MemoryOrderRelaxed)
+  if (PNaClMemoryOrderSeqCstOnly || AO == NaCl::MemoryOrderRelaxed)
     AO = NaCl::MemoryOrderSequentiallyConsistent;
 
   return ConstantInt::get(Type::getInt32Ty(C), AO);
 }
 
 std::pair<ConstantInt *, ConstantInt *>
 AtomicVisitor::freezeMemoryOrder(const AtomicCmpXchgInst &I, AtomicOrdering S,
                                  AtomicOrdering F) const {
   if (S == Release || (S == AcquireRelease && F != Acquire))
     // According to C++11's [atomics.types.operations.req], cmpxchg with release
@@ skipping 207 matching lines @@
                                         ArrayRef<Value *>());
   } else {
     const NaCl::AtomicIntrinsics::AtomicIntrinsic *Intrinsic =
         findAtomicIntrinsic(I, Intrinsic::nacl_atomic_fence, T);
     Value *Args[] = {freezeMemoryOrder(I, I.getOrdering())};
     replaceInstructionWithIntrinsicCall(I, Intrinsic, T, T, Args);
   }
 }
 
 ModulePass *llvm::createRewriteAtomicsPass() { return new RewriteAtomics(); }