[turbofan] Improve code generation for unordered comparisons.

test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "test/unittests/compiler/instruction-selector-unittest.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
@@ skipping 44 matching lines @@
       break;
 
     default:
       UNIMPLEMENTED();
   }
   return NULL;
 }
 
 
 // ARM64 logical instructions.
-static const MachInst2 kLogicalInstructions[] = {
+const MachInst2 kLogicalInstructions[] = {
     {&RawMachineAssembler::Word32And, "Word32And", kArm64And32, kMachInt32},
     {&RawMachineAssembler::Word64And, "Word64And", kArm64And, kMachInt64},
     {&RawMachineAssembler::Word32Or, "Word32Or", kArm64Or32, kMachInt32},
     {&RawMachineAssembler::Word64Or, "Word64Or", kArm64Or, kMachInt64},
     {&RawMachineAssembler::Word32Xor, "Word32Xor", kArm64Eor32, kMachInt32},
     {&RawMachineAssembler::Word64Xor, "Word64Xor", kArm64Eor, kMachInt64}};
 
 
 // ARM64 logical immediates: contiguous set bits, rotated about a power of two
 // sized block. The block is then duplicated across the word. Below is a random
 // subset of the 32-bit immediates.
-static const uint32_t kLogical32Immediates[] = {
+const uint32_t kLogical32Immediates[] = {
     0x00000002, 0x00000003, 0x00000070, 0x00000080, 0x00000100, 0x000001c0,
     0x00000300, 0x000007e0, 0x00003ffc, 0x00007fc0, 0x0003c000, 0x0003f000,
     0x0003ffc0, 0x0003fff8, 0x0007ff00, 0x0007ffe0, 0x000e0000, 0x001e0000,
     0x001ffffc, 0x003f0000, 0x003f8000, 0x00780000, 0x007fc000, 0x00ff0000,
     0x01800000, 0x01800180, 0x01f801f8, 0x03fe0000, 0x03ffffc0, 0x03fffffc,
     0x06000000, 0x07fc0000, 0x07ffc000, 0x07ffffc0, 0x07ffffe0, 0x0ffe0ffe,
     0x0ffff800, 0x0ffffff0, 0x0fffffff, 0x18001800, 0x1f001f00, 0x1f801f80,
     0x30303030, 0x3ff03ff0, 0x3ff83ff8, 0x3fff0000, 0x3fff8000, 0x3fffffc0,
     0x70007000, 0x7f7f7f7f, 0x7fc00000, 0x7fffffc0, 0x8000001f, 0x800001ff,
     0x81818181, 0x9fff9fff, 0xc00007ff, 0xc0ffffff, 0xdddddddd, 0xe00001ff,
     0xe00003ff, 0xe007ffff, 0xefffefff, 0xf000003f, 0xf001f001, 0xf3fff3ff,
     0xf800001f, 0xf80fffff, 0xf87ff87f, 0xfbfbfbfb, 0xfc00001f, 0xfc0000ff,
     0xfc0001ff, 0xfc03fc03, 0xfe0001ff, 0xff000001, 0xff03ff03, 0xff800000,
     0xff800fff, 0xff801fff, 0xff87ffff, 0xffc0003f, 0xffc007ff, 0xffcfffcf,
     0xffe00003, 0xffe1ffff, 0xfff0001f, 0xfff07fff, 0xfff80007, 0xfff87fff,
     0xfffc00ff, 0xfffe07ff, 0xffff00ff, 0xffffc001, 0xfffff007, 0xfffff3ff,
     0xfffff807, 0xfffff9ff, 0xfffffc0f, 0xfffffeff};
 
 
 // Random subset of 64-bit logical immediates.
-static const uint64_t kLogical64Immediates[] = {
+const uint64_t kLogical64Immediates[] = {
     0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
     0x0000000000000070, 0x0000000000000080, 0x0000000000000100,
     0x00000000000001c0, 0x0000000000000300, 0x0000000000000600,
     0x00000000000007e0, 0x0000000000003ffc, 0x0000000000007fc0,
     0x0000000600000000, 0x0000003ffffffffc, 0x000000f000000000,
     0x000001f800000000, 0x0003fc0000000000, 0x0003fc000003fc00,
     0x0003ffffffc00000, 0x0003ffffffffffc0, 0x0006000000060000,
     0x003ffffffffc0000, 0x0180018001800180, 0x01f801f801f801f8,
     0x0600000000000000, 0x1000000010000000, 0x1000100010001000,
     0x1010101010101010, 0x1111111111111111, 0x1f001f001f001f00,
@@ skipping 15 matching lines @@
   MachInst2 mi;
   ArchOpcode negate_arch_opcode;
 };
 
 
 std::ostream& operator<<(std::ostream& os, const AddSub& op) {
   return os << op.mi;
 }
 
 
-static const AddSub kAddSubInstructions[] = {
+const AddSub kAddSubInstructions[] = {
     {{&RawMachineAssembler::Int32Add, "Int32Add", kArm64Add32, kMachInt32},
      kArm64Sub32},
     {{&RawMachineAssembler::Int64Add, "Int64Add", kArm64Add, kMachInt64},
      kArm64Sub},
     {{&RawMachineAssembler::Int32Sub, "Int32Sub", kArm64Sub32, kMachInt32},
      kArm64Add32},
     {{&RawMachineAssembler::Int64Sub, "Int64Sub", kArm64Sub, kMachInt64},
      kArm64Add}};
 
 
 // ARM64 Add/Sub immediates: 12-bit immediate optionally shifted by 12.
 // Below is a combination of a random subset and some edge values.
-static const int32_t kAddSubImmediates[] = {
+const int32_t kAddSubImmediates[] = {
     0,        1,        69,       493,      599,      701,      719,
     768,      818,      842,      945,      1246,     1286,     1429,
     1669,     2171,     2179,     2182,     2254,     2334,     2338,
     2343,     2396,     2449,     2610,     2732,     2855,     2876,
     2944,     3377,     3458,     3475,     3476,     3540,     3574,
     3601,     3813,     3871,     3917,     4095,     4096,     16384,
     364544,   462848,   970752,   1523712,  1863680,  2363392,  3219456,
     3280896,  4247552,  4526080,  4575232,  4960256,  5505024,  5894144,
     6004736,  6193152,  6385664,  6795264,  7114752,  7233536,  7348224,
     7499776,  7573504,  7729152,  8634368,  8937472,  9465856,  10354688,
     10682368, 11059200, 11460608, 13168640, 13176832, 14336000, 15028224,
     15597568, 15892480, 16773120};
 
 
 // ARM64 flag setting data processing instructions.
-static const MachInst2 kDPFlagSetInstructions[] = {
+const MachInst2 kDPFlagSetInstructions[] = {
     {&RawMachineAssembler::Word32And, "Word32And", kArm64Tst32, kMachInt32},
     {&RawMachineAssembler::Int32Add, "Int32Add", kArm64Cmn32, kMachInt32},
     {&RawMachineAssembler::Int32Sub, "Int32Sub", kArm64Cmp32, kMachInt32},
     {&RawMachineAssembler::Word64And, "Word64And", kArm64Tst, kMachInt64}};
 
 
 // ARM64 arithmetic with overflow instructions.
-static const MachInst2 kOvfAddSubInstructions[] = {
+const MachInst2 kOvfAddSubInstructions[] = {
     {&RawMachineAssembler::Int32AddWithOverflow, "Int32AddWithOverflow",
      kArm64Add32, kMachInt32},
     {&RawMachineAssembler::Int32SubWithOverflow, "Int32SubWithOverflow",
      kArm64Sub32, kMachInt32}};
 
 
 // ARM64 shift instructions.
-static const Shift kShiftInstructions[] = {
+const Shift kShiftInstructions[] = {
     {{&RawMachineAssembler::Word32Shl, "Word32Shl", kArm64Lsl32, kMachInt32},
      kMode_Operand2_R_LSL_I},
     {{&RawMachineAssembler::Word64Shl, "Word64Shl", kArm64Lsl, kMachInt64},
      kMode_Operand2_R_LSL_I},
     {{&RawMachineAssembler::Word32Shr, "Word32Shr", kArm64Lsr32, kMachInt32},
      kMode_Operand2_R_LSR_I},
     {{&RawMachineAssembler::Word64Shr, "Word64Shr", kArm64Lsr, kMachInt64},
      kMode_Operand2_R_LSR_I},
     {{&RawMachineAssembler::Word32Sar, "Word32Sar", kArm64Asr32, kMachInt32},
      kMode_Operand2_R_ASR_I},
     {{&RawMachineAssembler::Word64Sar, "Word64Sar", kArm64Asr, kMachInt64},
      kMode_Operand2_R_ASR_I},
     {{&RawMachineAssembler::Word32Ror, "Word32Ror", kArm64Ror32, kMachInt32},
      kMode_Operand2_R_ROR_I},
     {{&RawMachineAssembler::Word64Ror, "Word64Ror", kArm64Ror, kMachInt64},
      kMode_Operand2_R_ROR_I}};
 
 
 // ARM64 Mul/Div instructions.
-static const MachInst2 kMulDivInstructions[] = {
+const MachInst2 kMulDivInstructions[] = {
     {&RawMachineAssembler::Int32Mul, "Int32Mul", kArm64Mul32, kMachInt32},
     {&RawMachineAssembler::Int64Mul, "Int64Mul", kArm64Mul, kMachInt64},
     {&RawMachineAssembler::Int32Div, "Int32Div", kArm64Idiv32, kMachInt32},
     {&RawMachineAssembler::Int64Div, "Int64Div", kArm64Idiv, kMachInt64},
     {&RawMachineAssembler::Uint32Div, "Uint32Div", kArm64Udiv32, kMachInt32},
     {&RawMachineAssembler::Uint64Div, "Uint64Div", kArm64Udiv, kMachInt64}};
 
 
 // ARM64 FP arithmetic instructions.
-static const MachInst2 kFPArithInstructions[] = {
+const MachInst2 kFPArithInstructions[] = {
     {&RawMachineAssembler::Float64Add, "Float64Add", kArm64Float64Add,
      kMachFloat64},
     {&RawMachineAssembler::Float64Sub, "Float64Sub", kArm64Float64Sub,
      kMachFloat64},
     {&RawMachineAssembler::Float64Mul, "Float64Mul", kArm64Float64Mul,
      kMachFloat64},
     {&RawMachineAssembler::Float64Div, "Float64Div", kArm64Float64Div,
      kMachFloat64}};
 
 
 struct FPCmp {
   MachInst2 mi;
   FlagsCondition cond;
 };
 
 
 std::ostream& operator<<(std::ostream& os, const FPCmp& cmp) {
   return os << cmp.mi;
 }
 
 
 // ARM64 FP comparison instructions.
-static const FPCmp kFPCmpInstructions[] = {
+const FPCmp kFPCmpInstructions[] = {
     {{&RawMachineAssembler::Float64Equal, "Float64Equal", kArm64Float64Cmp,
       kMachFloat64},
-     kUnorderedEqual},
+     kEqual},
     {{&RawMachineAssembler::Float64LessThan, "Float64LessThan",
       kArm64Float64Cmp, kMachFloat64},
-     kUnorderedLessThan},
+     kUnsignedLessThan},
     {{&RawMachineAssembler::Float64LessThanOrEqual, "Float64LessThanOrEqual",
       kArm64Float64Cmp, kMachFloat64},
-     kUnorderedLessThanOrEqual}};
+     kUnsignedLessThanOrEqual}};
 
 
 struct Conversion {
   // The machine_type field in MachInst1 represents the destination type.
   MachInst1 mi;
   MachineType src_machine_type;
 };
 
 
 std::ostream& operator<<(std::ostream& os, const Conversion& conv) {
   return os << conv.mi;
 }
 
 
 // ARM64 type conversion instructions.
-static const Conversion kConversionInstructions[] = {
+const Conversion kConversionInstructions[] = {
     {{&RawMachineAssembler::ChangeFloat32ToFloat64, "ChangeFloat32ToFloat64",
       kArm64Float32ToFloat64, kMachFloat64},
      kMachFloat32},
     {{&RawMachineAssembler::TruncateFloat64ToFloat32,
       "TruncateFloat64ToFloat32", kArm64Float64ToFloat32, kMachFloat32},
      kMachFloat64},
     {{&RawMachineAssembler::ChangeInt32ToInt64, "ChangeInt32ToInt64",
       kArm64Sxtw, kMachInt64},
      kMachInt32},
     {{&RawMachineAssembler::ChangeUint32ToUint64, "ChangeUint32ToUint64",
@@ skipping 1899 matching lines @@
     ASSERT_EQ(1U, s[0]->InputCount());
     EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
     ASSERT_EQ(1U, s[0]->OutputCount());
     EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
   }
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8