Subzero: Use SmallVector<> instead of vector<> in a couple places.

src/IceRegAlloc.cpp

 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the LinearScan class, which performs the
 // linear-scan register allocation after liveness analysis has been
 // performed.
 //
 //===----------------------------------------------------------------------===//
 
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceInst.h"
 #include "IceOperand.h"
 #include "IceRegAlloc.h"
 #include "IceTargetLowering.h"
 
 namespace Ice {
 
 namespace {
 
+// TODO(stichnot): Statically choose the size based on the target
+// being compiled.
+const size_t REGS_SIZE = 32;
+
 // Returns true if Var has any definitions within Item's live range.
 // TODO(stichnot): Consider trimming the Definitions list similar to
 // how the live ranges are trimmed, since all the overlapsDefs() tests
 // are whether some variable's definitions overlap Cur, and trimming
 // is with respect Cur.start.  Initial tests show no measurable
 // performance difference, so we'll keep the code simple for now.
 bool overlapsDefs(const Cfg *Func, const Variable *Item, const Variable *Var) {
   const bool UseTrimmed = true;
   VariablesMetadata *VMetadata = Func->getVMetadata();
   if (const Inst *FirstDef = VMetadata->getFirstDefinition(Var))
@@ skipping 236 matching lines @@
     }
   }
 
   // Build a LiveRange representing the Kills list.
   LiveRange KillsRange(Kills);
   KillsRange.untrim();
 
   // RegUses[I] is the number of live ranges (variables) that register
   // I is currently assigned to.  It can be greater than 1 as a result
   // of AllowOverlap inference below.
-  std::vector<int> RegUses(NumRegisters);
+  llvm::SmallVector<int, REGS_SIZE> RegUses(NumRegisters);
   // Unhandled is already set to all ranges in increasing order of
   // start points.
   assert(Active.empty());
   assert(Inactive.empty());
   assert(Handled.empty());
   const TargetLowering::RegSetMask RegsInclude =
       TargetLowering::RegSet_CallerSave;
   const TargetLowering::RegSetMask RegsExclude = TargetLowering::RegSet_None;
   const llvm::SmallBitVector KillsMask =
       Func->getTarget()->getRegisterSet(RegsInclude, RegsExclude);
@@ skipping 183 matching lines @@
       for (const Variable *Item : Active) {
         int32_t RegNum = Item->getRegNumTmp();
         if (Item != Prefer && RegNum == PreferReg &&
             overlapsDefs(Func, Cur, Item)) {
           AllowOverlap = false;
           dumpDisableOverlap(Func, Item, "Active");
         }
       }
     }
 
-    std::vector<RegWeight> Weights(RegMask.size());
+    llvm::SmallVector<RegWeight, REGS_SIZE> Weights(RegMask.size());
 
     // Remove registers from the Free[] list where an Unhandled
     // precolored range overlaps with the current range, and set those
     // registers to infinite weight so that they aren't candidates for
     // eviction.  Cur->rangeEndsBefore(Item) is an early exit check
     // that turns a guaranteed O(N^2) algorithm into expected linear
     // complexity.
     llvm::SmallBitVector PrecoloredUnhandledMask(RegMask.size());
     // Note: PrecoloredUnhandledMask is only used for dumping.
     for (Variable *Item : reverse_range(UnhandledPrecolored)) {
@@ skipping 161 matching lines @@
   }
   // Move anything Active or Inactive to Handled for easier handling.
   for (Variable *I : Active)
     Handled.push_back(I);
   Active.clear();
   for (Variable *I : Inactive)
     Handled.push_back(I);
   Inactive.clear();
   dump(Func);
 
-  // TODO(stichnot): Statically choose the size based on the target
-  // being compiled.
-  const size_t REGS_SIZE = 32;
   llvm::SmallVector<int32_t, REGS_SIZE> Permutation(NumRegisters);
   if (Randomized) {
     Func->getTarget()->makeRandomRegisterPermutation(
         Permutation, PreDefinedRegisters | ~RegMaskFull);
   }
 
   // Finish up by assigning RegNumTmp->RegNum (or a random permutation
   // thereof) for each Variable.
   for (Variable *Item : Handled) {
     int32_t RegNum = Item->getRegNumTmp();
@@ skipping 57 matching lines @@
     Str << "\n";
   }
   Str << "++++++ Inactive:\n";
   for (const Variable *Item : Inactive) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
 }
 
 } // end of namespace Ice