Subzero: Add locking to prepare for multithreaded translation.

src/IceRegAlloc.cpp

 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the LinearScan class, which performs the
@@ skipping 246 matching lines @@
 // two interfering variables to share the same register in certain
 // cases.
 //
 // Requires running Cfg::liveness(Liveness_Intervals) in
 // preparation.  Results are assigned to Variable::RegNum for each
 // Variable.
 void LinearScan::scan(const llvm::SmallBitVector &RegMaskFull,
                       bool Randomized) {
   TimerMarker T(TimerStack::TT_linearScan, Func);
   assert(RegMaskFull.any()); // Sanity check
-  Ostream &Str = Func->getContext()->getStrDump();
+  GlobalContext *Ctx = Func->getContext();
   const bool Verbose =
-      ALLOW_DUMP && Func->getContext()->isVerbose(IceV_LinearScan);
+      ALLOW_DUMP && Ctx->isVerbose(IceV_LinearScan);
+  if (Verbose)
+    Ctx->lockStr();
   Func->resetCurrentNode();
   VariablesMetadata *VMetadata = Func->getVMetadata();
   const size_t NumRegisters = RegMaskFull.size();
   llvm::SmallBitVector PreDefinedRegisters(NumRegisters);
   if (Randomized) {
     for (Variable *Var : UnhandledPrecolored) {
       PreDefinedRegisters[Var->getRegNum()] = true;
     }
   }
 
@@ skipping 13 matching lines @@
   const TargetLowering::RegSetMask RegsInclude =
       TargetLowering::RegSet_CallerSave;
   const TargetLowering::RegSetMask RegsExclude = TargetLowering::RegSet_None;
   const llvm::SmallBitVector KillsMask =
       Func->getTarget()->getRegisterSet(RegsInclude, RegsExclude);
 
   while (!Unhandled.empty()) {
     Variable *Cur = Unhandled.back();
     Unhandled.pop_back();
     if (Verbose) {
+      Ostream &Str = Ctx->getStrDump();
       Str << "\nConsidering  ";
       dumpLiveRange(Cur, Func);
       Str << "\n";
     }
     const llvm::SmallBitVector RegMask =
         RegMaskFull & Func->getTarget()->getRegisterSetForType(Cur->getType());
     KillsRange.trim(Cur->getLiveRange().getStart());
 
     // Check for precolored ranges.  If Cur is precolored, it
     // definitely gets that register.  Previously processed live
     // ranges would have avoided that register due to it being
     // precolored.  Future processed live ranges won't evict that
     // register because the live range has infinite weight.
     if (Cur->hasReg()) {
       int32_t RegNum = Cur->getRegNum();
       // RegNumTmp should have already been set above.
       assert(Cur->getRegNumTmp() == RegNum);
       if (Verbose) {
+        Ostream &Str = Ctx->getStrDump();
         Str << "Precoloring  ";
         dumpLiveRange(Cur, Func);
         Str << "\n";
       }
       Active.push_back(Cur);
       assert(RegUses[RegNum] >= 0);
       ++RegUses[RegNum];
       assert(!UnhandledPrecolored.empty());
       assert(UnhandledPrecolored.back() == Cur);
       UnhandledPrecolored.pop_back();
       continue;
     }
 
     // Check for active ranges that have expired or become inactive.
     for (SizeT I = Active.size(); I > 0; --I) {
       const SizeT Index = I - 1;
       Variable *Item = Active[Index];
       Item->trimLiveRange(Cur->getLiveRange().getStart());
       bool Moved = false;
       if (Item->rangeEndsBefore(Cur)) {
         // Move Item from Active to Handled list.
         if (Verbose) {
+          Ostream &Str = Ctx->getStrDump();
           Str << "Expiring     ";
           dumpLiveRange(Item, Func);
           Str << "\n";
         }
         moveItem(Active, Index, Handled);
         Moved = true;
       } else if (!Item->rangeOverlapsStart(Cur)) {
         // Move Item from Active to Inactive list.
         if (Verbose) {
+          Ostream &Str = Ctx->getStrDump();
           Str << "Inactivating ";
           dumpLiveRange(Item, Func);
           Str << "\n";
         }
         moveItem(Active, Index, Inactive);
         Moved = true;
       }
       if (Moved) {
         // Decrement Item from RegUses[].
         assert(Item->hasRegTmp());
         int32_t RegNum = Item->getRegNumTmp();
         --RegUses[RegNum];
         assert(RegUses[RegNum] >= 0);
       }
     }
 
     // Check for inactive ranges that have expired or reactivated.
     for (SizeT I = Inactive.size(); I > 0; --I) {
       const SizeT Index = I - 1;
       Variable *Item = Inactive[Index];
       Item->trimLiveRange(Cur->getLiveRange().getStart());
       if (Item->rangeEndsBefore(Cur)) {
         // Move Item from Inactive to Handled list.
         if (Verbose) {
+          Ostream &Str = Ctx->getStrDump();
           Str << "Expiring     ";
           dumpLiveRange(Item, Func);
           Str << "\n";
         }
         moveItem(Inactive, Index, Handled);
       } else if (Item->rangeOverlapsStart(Cur)) {
         // Move Item from Inactive to Active list.
         if (Verbose) {
+          Ostream &Str = Ctx->getStrDump();
           Str << "Reactivating ";
           dumpLiveRange(Item, Func);
           Str << "\n";
         }
         moveItem(Inactive, Index, Active);
         // Increment Item in RegUses[].
         assert(Item->hasRegTmp());
         int32_t RegNum = Item->getRegNumTmp();
         assert(RegUses[RegNum] >= 0);
         ++RegUses[RegNum];
@@ skipping 45 matching lines @@
                     IsSingleDef && IsAssign && !overlapsDefs(Func, Cur, SrcVar);
               }
               if (AllowOverlap || Free[SrcReg]) {
                 Prefer = SrcVar;
                 PreferReg = SrcReg;
               }
             }
           }
         }
         if (Verbose && Prefer) {
+          Ostream &Str = Ctx->getStrDump();
           Str << "Initial Prefer=";
           Prefer->dump(Func);
           Str << " R=" << PreferReg << " LIVE=" << Prefer->getLiveRange()
               << " Overlap=" << AllowOverlap << "\n";
         }
       }
     }
 
     // Remove registers from the Free[] list where an Inactive range
     // overlaps with the current range.
@@ skipping 65 matching lines @@
       for (int i = KillsMask.find_first(); i != -1;
            i = KillsMask.find_next(i)) {
         Weights[i].setWeight(RegWeight::Inf);
         if (PreferReg == i)
           AllowOverlap = false;
       }
     }
 
     // Print info about physical register availability.
     if (Verbose) {
+      Ostream &Str = Ctx->getStrDump();
       for (SizeT i = 0; i < RegMask.size(); ++i) {
         if (RegMask[i]) {
           Str << Func->getTarget()->getRegName(i, IceType_i32)
               << "(U=" << RegUses[i] << ",F=" << Free[i]
               << ",P=" << PrecoloredUnhandledMask[i] << ") ";
         }
       }
       Str << "\n";
     }
 
     if (Prefer && (AllowOverlap || Free[PreferReg])) {
       // First choice: a preferred register that is either free or is
       // allowed to overlap with its linked variable.
       Cur->setRegNumTmp(PreferReg);
       if (Verbose) {
+        Ostream &Str = Ctx->getStrDump();
         Str << "Preferring   ";
         dumpLiveRange(Cur, Func);
         Str << "\n";
       }
       assert(RegUses[PreferReg] >= 0);
       ++RegUses[PreferReg];
       Active.push_back(Cur);
     } else if (Free.any()) {
       // Second choice: any free register.  TODO: After explicit
       // affinity is considered, is there a strategy better than just
       // picking the lowest-numbered available register?
       int32_t RegNum = Free.find_first();
       Cur->setRegNumTmp(RegNum);
       if (Verbose) {
+        Ostream &Str = Ctx->getStrDump();
         Str << "Allocating   ";
         dumpLiveRange(Cur, Func);
         Str << "\n";
       }
       assert(RegUses[RegNum] >= 0);
       ++RegUses[RegNum];
       Active.push_back(Cur);
     } else {
       // Fallback: there are no free registers, so we look for the
       // lowest-weight register and see if Cur has higher weight.
@@ skipping 33 matching lines @@
                          "infinite-weight live range");
         }
       } else {
         // Evict all live ranges in Active that register number
         // MinWeightIndex is assigned to.
         for (SizeT I = Active.size(); I > 0; --I) {
           const SizeT Index = I - 1;
           Variable *Item = Active[Index];
           if (Item->getRegNumTmp() == MinWeightIndex) {
             if (Verbose) {
+              Ostream &Str = Ctx->getStrDump();
               Str << "Evicting     ";
               dumpLiveRange(Item, Func);
               Str << "\n";
             }
             --RegUses[MinWeightIndex];
             assert(RegUses[MinWeightIndex] >= 0);
             Item->setRegNumTmp(Variable::NoRegister);
             moveItem(Active, Index, Handled);
           }
         }
         // Do the same for Inactive.
         for (SizeT I = Inactive.size(); I > 0; --I) {
           const SizeT Index = I - 1;
           Variable *Item = Inactive[Index];
           // Note: The Item->rangeOverlaps(Cur) clause is not part of the
           // description of AssignMemLoc() in the original paper.  But
           // there doesn't seem to be any need to evict an inactive
           // live range that doesn't overlap with the live range
           // currently being considered.  It's especially bad if we
           // would end up evicting an infinite-weight but
           // currently-inactive live range.  The most common situation
           // for this would be a scratch register kill set for call
           // instructions.
           if (Item->getRegNumTmp() == MinWeightIndex &&
               Item->rangeOverlaps(Cur)) {
             if (Verbose) {
+              Ostream &Str = Ctx->getStrDump();
               Str << "Evicting     ";
               dumpLiveRange(Item, Func);
               Str << "\n";
             }
             Item->setRegNumTmp(Variable::NoRegister);
             moveItem(Inactive, Index, Handled);
           }
         }
         // Assign the register to Cur.
         Cur->setRegNumTmp(MinWeightIndex);
         assert(RegUses[MinWeightIndex] >= 0);
         ++RegUses[MinWeightIndex];
         Active.push_back(Cur);
         if (Verbose) {
+          Ostream &Str = Ctx->getStrDump();
           Str << "Allocating   ";
           dumpLiveRange(Cur, Func);
           Str << "\n";
         }
       }
     }
     dump(Func);
   }
   // Move anything Active or Inactive to Handled for easier handling.
   for (Variable *I : Active)
@@ skipping 13 matching lines @@
   // Finish up by assigning RegNumTmp->RegNum (or a random permutation
   // thereof) for each Variable.
   for (Variable *Item : Handled) {
     int32_t RegNum = Item->getRegNumTmp();
     int32_t AssignedRegNum = RegNum;
 
     if (Randomized && Item->hasRegTmp() && !Item->hasReg()) {
       AssignedRegNum = Permutation[RegNum];
     }
     if (Verbose) {
+      Ostream &Str = Ctx->getStrDump();
       if (!Item->hasRegTmp()) {
         Str << "Not assigning ";
         Item->dump(Func);
         Str << "\n";
       } else {
         Str << (AssignedRegNum == Item->getRegNum() ? "Reassigning "
                                                     : "Assigning ")
             << Func->getTarget()->getRegName(AssignedRegNum, IceType_i32)
             << "(r" << AssignedRegNum << ") to ";
         Item->dump(Func);
         Str << "\n";
       }
     }
     Item->setRegNum(AssignedRegNum);
   }
 
   // TODO: Consider running register allocation one more time, with
   // infinite registers, for two reasons.  First, evicted live ranges
   // get a second chance for a register.  Second, it allows coalescing
   // of stack slots.  If there is no time budget for the second
   // register allocation run, each unallocated variable just gets its
   // own slot.
   //
   // Another idea for coalescing stack slots is to initialize the
   // Unhandled list with just the unallocated variables, saving time
   // but not offering second-chance opportunities.
+
+  if (Verbose)
+    Ctx->unlockStr();
 }
 
 // ======================== Dump routines ======================== //
 
 void LinearScan::dump(Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
-  Ostream &Str = Func->getContext()->getStrDump();
   if (!Func->getContext()->isVerbose(IceV_LinearScan))
     return;
+  Ostream &Str = Func->getContext()->getStrDump();
   Func->resetCurrentNode();
   Str << "**** Current regalloc state:\n";
   Str << "++++++ Handled:\n";
   for (const Variable *Item : Handled) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Unhandled:\n";
   for (const Variable *Item : reverse_range(Unhandled)) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Active:\n";
   for (const Variable *Item : Active) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Inactive:\n";
   for (const Variable *Item : Inactive) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
 }
 
 } // end of namespace Ice