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Side by Side Diff: src/IceInstX8632.cpp

Issue 837553009: Make fixups reference any constant (allow const float/double pool literals). (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: go back to one arenaallocator type alias Created 5 years, 11 months ago
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1 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===// 1 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the InstX8632 and OperandX8632 classes, 10 // This file implements the InstX8632 and OperandX8632 classes,
(...skipping 569 matching lines...) Expand 10 before | Expand all | Expand 10 after
580 (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr); 580 (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
581 } 581 }
582 } else if (const auto Mem = llvm::dyn_cast<OperandX8632Mem>(Src)) { 582 } else if (const auto Mem = llvm::dyn_cast<OperandX8632Mem>(Src)) {
583 Mem->emitSegmentOverride(Asm); 583 Mem->emitSegmentOverride(Asm);
584 (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm)); 584 (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
585 } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) { 585 } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
586 (Asm->*(Emitter.GPRImm))(Ty, VarReg, x86::Immediate(Imm->getValue())); 586 (Asm->*(Emitter.GPRImm))(Ty, VarReg, x86::Immediate(Imm->getValue()));
587 } else if (const auto Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) { 587 } else if (const auto Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
588 AssemblerFixup *Fixup = 588 AssemblerFixup *Fixup =
589 x86::DisplacementRelocation::create(Asm, FK_Abs_4, Reloc); 589 x86::DisplacementRelocation::create(Asm, FK_Abs_4, Reloc);
590 (Asm->*(Emitter.GPRImm))(Ty, VarReg, x86::Immediate(Fixup)); 590 (Asm->*(Emitter.GPRImm))(Ty, VarReg,
591 x86::Immediate(Reloc->getOffset(), Fixup));
591 } else if (const auto Split = llvm::dyn_cast<VariableSplit>(Src)) { 592 } else if (const auto Split = llvm::dyn_cast<VariableSplit>(Src)) {
592 (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Func)); 593 (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Func));
593 } else { 594 } else {
594 llvm_unreachable("Unexpected operand type"); 595 llvm_unreachable("Unexpected operand type");
595 } 596 }
596 } 597 }
597 598
598 void emitIASAddrOpTyGPR(const Cfg *Func, Type Ty, const x86::Address &Addr, 599 void emitIASAddrOpTyGPR(const Cfg *Func, Type Ty, const x86::Address &Addr,
599 const Operand *Src, 600 const Operand *Src,
600 const x86::AssemblerX86::GPREmitterAddrOp &Emitter) { 601 const x86::AssemblerX86::GPREmitterAddrOp &Emitter) {
601 x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>(); 602 x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
602 // Src can only be Reg or Immediate. 603 // Src can only be Reg or Immediate.
603 if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) { 604 if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
604 assert(SrcVar->hasReg()); 605 assert(SrcVar->hasReg());
605 RegX8632::GPRRegister SrcReg = 606 RegX8632::GPRRegister SrcReg =
606 RegX8632::getEncodedByteRegOrGPR(Ty, SrcVar->getRegNum()); 607 RegX8632::getEncodedByteRegOrGPR(Ty, SrcVar->getRegNum());
607 (Asm->*(Emitter.AddrGPR))(Ty, Addr, SrcReg); 608 (Asm->*(Emitter.AddrGPR))(Ty, Addr, SrcReg);
608 } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) { 609 } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
609 (Asm->*(Emitter.AddrImm))(Ty, Addr, x86::Immediate(Imm->getValue())); 610 (Asm->*(Emitter.AddrImm))(Ty, Addr, x86::Immediate(Imm->getValue()));
610 } else if (const auto Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) { 611 } else if (const auto Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
611 AssemblerFixup *Fixup = 612 AssemblerFixup *Fixup =
612 x86::DisplacementRelocation::create(Asm, FK_Abs_4, Reloc); 613 x86::DisplacementRelocation::create(Asm, FK_Abs_4, Reloc);
613 (Asm->*(Emitter.AddrImm))(Ty, Addr, x86::Immediate(Fixup)); 614 (Asm->*(Emitter.AddrImm))(Ty, Addr,
615 x86::Immediate(Reloc->getOffset(), Fixup));
614 } else { 616 } else {
615 llvm_unreachable("Unexpected operand type"); 617 llvm_unreachable("Unexpected operand type");
616 } 618 }
617 } 619 }
618 620
619 void emitIASAsAddrOpTyGPR(const Cfg *Func, Type Ty, const Operand *Op0, 621 void emitIASAsAddrOpTyGPR(const Cfg *Func, Type Ty, const Operand *Op0,
620 const Operand *Op1, 622 const Operand *Op1,
621 const x86::AssemblerX86::GPREmitterAddrOp &Emitter) { 623 const x86::AssemblerX86::GPREmitterAddrOp &Emitter) {
622 if (const auto Op0Var = llvm::dyn_cast<Variable>(Op0)) { 624 if (const auto Op0Var = llvm::dyn_cast<Variable>(Op0)) {
623 assert(!Op0Var->hasReg()); 625 assert(!Op0Var->hasReg());
(...skipping 96 matching lines...) Expand 10 before | Expand all | Expand 10 after
720 (Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg); 722 (Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
721 } else { 723 } else {
722 x86::Address SrcStackAddr = static_cast<TargetX8632 *>(Func->getTarget()) 724 x86::Address SrcStackAddr = static_cast<TargetX8632 *>(Func->getTarget())
723 ->stackVarToAsmOperand(SrcVar); 725 ->stackVarToAsmOperand(SrcVar);
724 (Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr); 726 (Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
725 } 727 }
726 } else if (const auto Mem = llvm::dyn_cast<OperandX8632Mem>(Src)) { 728 } else if (const auto Mem = llvm::dyn_cast<OperandX8632Mem>(Src)) {
727 assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment); 729 assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
728 (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm)); 730 (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
729 } else if (const auto Imm = llvm::dyn_cast<Constant>(Src)) { 731 } else if (const auto Imm = llvm::dyn_cast<Constant>(Src)) {
730 (Asm->*(Emitter.XmmAddr))( 732 (Asm->*(Emitter.XmmAddr))(Ty, VarReg, x86::Address::ofConstPool(Asm, Imm));
731 Ty, VarReg, x86::Address::ofConstPool(Func->getContext(), Asm, Imm));
732 } else { 733 } else {
733 llvm_unreachable("Unexpected operand type"); 734 llvm_unreachable("Unexpected operand type");
734 } 735 }
735 } 736 }
736 737
737 template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(int32_t), 738 template <typename DReg_t, typename SReg_t, DReg_t (*destEnc)(int32_t),
738 SReg_t (*srcEnc)(int32_t)> 739 SReg_t (*srcEnc)(int32_t)>
739 void emitIASCastRegOp( 740 void emitIASCastRegOp(
740 const Cfg *Func, Type DispatchTy, const Variable *Dest, const Operand *Src, 741 const Cfg *Func, Type DispatchTy, const Variable *Dest, const Operand *Src,
741 const x86::AssemblerX86::CastEmitterRegOp<DReg_t, SReg_t> Emitter) { 742 const x86::AssemblerX86::CastEmitterRegOp<DReg_t, SReg_t> Emitter) {
(...skipping 1570 matching lines...) Expand 10 before | Expand all | Expand 10 after
2312 Asm->add(IceType_i32, RegX8632::Encoded_Reg_esp, Width); 2313 Asm->add(IceType_i32, RegX8632::Encoded_Reg_esp, Width);
2313 } else { 2314 } else {
2314 x86::Address StackAddr(static_cast<TargetX8632 *>(Func->getTarget()) 2315 x86::Address StackAddr(static_cast<TargetX8632 *>(Func->getTarget())
2315 ->stackVarToAsmOperand(Var)); 2316 ->stackVarToAsmOperand(Var));
2316 Asm->fld(Ty, StackAddr); 2317 Asm->fld(Ty, StackAddr);
2317 } 2318 }
2318 } else if (const auto Mem = llvm::dyn_cast<OperandX8632Mem>(Src)) { 2319 } else if (const auto Mem = llvm::dyn_cast<OperandX8632Mem>(Src)) {
2319 assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment); 2320 assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
2320 Asm->fld(Ty, Mem->toAsmAddress(Asm)); 2321 Asm->fld(Ty, Mem->toAsmAddress(Asm));
2321 } else if (const auto Imm = llvm::dyn_cast<Constant>(Src)) { 2322 } else if (const auto Imm = llvm::dyn_cast<Constant>(Src)) {
2322 Asm->fld(Ty, x86::Address::ofConstPool(Func->getContext(), Asm, Imm)); 2323 Asm->fld(Ty, x86::Address::ofConstPool(Asm, Imm));
2323 } else { 2324 } else {
2324 llvm_unreachable("Unexpected operand type"); 2325 llvm_unreachable("Unexpected operand type");
2325 } 2326 }
2326 } 2327 }
2327 2328
2328 void InstX8632Fld::dump(const Cfg *Func) const { 2329 void InstX8632Fld::dump(const Cfg *Func) const {
2329 if (!ALLOW_DUMP) 2330 if (!ALLOW_DUMP)
2330 return; 2331 return;
2331 Ostream &Str = Func->getContext()->getStrDump(); 2332 Ostream &Str = Func->getContext()->getStrDump();
2332 Str << "fld." << getSrc(0)->getType() << " "; 2333 Str << "fld." << getSrc(0)->getType() << " ";
(...skipping 509 matching lines...) Expand 10 before | Expand all | Expand 10 after
2842 2843
2843 x86::Address OperandX8632Mem::toAsmAddress(Assembler *Asm) const { 2844 x86::Address OperandX8632Mem::toAsmAddress(Assembler *Asm) const {
2844 int32_t Disp = 0; 2845 int32_t Disp = 0;
2845 AssemblerFixup *Fixup = nullptr; 2846 AssemblerFixup *Fixup = nullptr;
2846 // Determine the offset (is it relocatable?) 2847 // Determine the offset (is it relocatable?)
2847 if (getOffset()) { 2848 if (getOffset()) {
2848 if (const auto CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) { 2849 if (const auto CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
2849 Disp = static_cast<int32_t>(CI->getValue()); 2850 Disp = static_cast<int32_t>(CI->getValue());
2850 } else if (const auto CR = 2851 } else if (const auto CR =
2851 llvm::dyn_cast<ConstantRelocatable>(getOffset())) { 2852 llvm::dyn_cast<ConstantRelocatable>(getOffset())) {
2853 Disp = CR->getOffset();
2852 Fixup = x86::DisplacementRelocation::create(Asm, FK_Abs_4, CR); 2854 Fixup = x86::DisplacementRelocation::create(Asm, FK_Abs_4, CR);
2853 } else { 2855 } else {
2854 llvm_unreachable("Unexpected offset type"); 2856 llvm_unreachable("Unexpected offset type");
2855 } 2857 }
2856 } 2858 }
2857 2859
2858 // Now convert to the various possible forms. 2860 // Now convert to the various possible forms.
2859 if (getBase() && getIndex()) { 2861 if (getBase() && getIndex()) {
2860 return x86::Address(RegX8632::getEncodedGPR(getBase()->getRegNum()), 2862 return x86::Address(RegX8632::getEncodedGPR(getBase()->getRegNum()),
2861 RegX8632::getEncodedGPR(getIndex()->getRegNum()), 2863 RegX8632::getEncodedGPR(getIndex()->getRegNum()),
2862 x86::ScaleFactor(getShift()), Disp); 2864 x86::ScaleFactor(getShift()), Disp);
2863 } else if (getBase()) { 2865 } else if (getBase()) {
2864 return x86::Address(RegX8632::getEncodedGPR(getBase()->getRegNum()), Disp); 2866 return x86::Address(RegX8632::getEncodedGPR(getBase()->getRegNum()), Disp);
2865 } else if (getIndex()) { 2867 } else if (getIndex()) {
2866 return x86::Address(RegX8632::getEncodedGPR(getIndex()->getRegNum()), 2868 return x86::Address(RegX8632::getEncodedGPR(getIndex()->getRegNum()),
2867 x86::ScaleFactor(getShift()), Disp); 2869 x86::ScaleFactor(getShift()), Disp);
2868 } else if (Fixup) { 2870 } else if (Fixup) {
2869 // The fixup itself has an offset, so Disp should still be 0. 2871 return x86::Address::Absolute(Disp, Fixup);
2870 assert(Disp == 0);
2871 return x86::Address::Absolute(Fixup);
2872 } else { 2872 } else {
2873 return x86::Address::Absolute(Disp); 2873 return x86::Address::Absolute(Disp);
2874 } 2874 }
2875 } 2875 }
2876 2876
2877 x86::Address VariableSplit::toAsmAddress(const Cfg *Func) const { 2877 x86::Address VariableSplit::toAsmAddress(const Cfg *Func) const {
2878 assert(!Var->hasReg()); 2878 assert(!Var->hasReg());
2879 const TargetLowering *Target = Func->getTarget(); 2879 const TargetLowering *Target = Func->getTarget();
2880 int32_t Offset = 2880 int32_t Offset =
2881 Var->getStackOffset() + Target->getStackAdjustment() + getOffset(); 2881 Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after
2914 } 2914 }
2915 Str << "("; 2915 Str << "(";
2916 if (Func) 2916 if (Func)
2917 Var->dump(Func); 2917 Var->dump(Func);
2918 else 2918 else
2919 Var->dump(Str); 2919 Var->dump(Str);
2920 Str << ")"; 2920 Str << ")";
2921 } 2921 }
2922 2922
2923 } // end of namespace Ice 2923 } // end of namespace Ice
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