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| 1 //===- subzero/src/llvm2ice.cpp - Driver for testing ----------------------===// | 1 //===- subzero/src/llvm2ice.cpp - Driver for testing ----------------------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file defines a driver that uses LLVM capabilities to parse a | 10 // This file defines a driver that uses LLVM capabilities to parse a |
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| 37 "verbose", cl::CommaSeparated, | 37 "verbose", cl::CommaSeparated, |
| 38 cl::desc("Verbose options (can be comma-separated):"), | 38 cl::desc("Verbose options (can be comma-separated):"), |
| 39 cl::values( | 39 cl::values( |
| 40 clEnumValN(Ice::IceV_Instructions, "inst", "Print basic instructions"), | 40 clEnumValN(Ice::IceV_Instructions, "inst", "Print basic instructions"), |
| 41 clEnumValN(Ice::IceV_Deleted, "del", "Include deleted instructions"), | 41 clEnumValN(Ice::IceV_Deleted, "del", "Include deleted instructions"), |
| 42 clEnumValN(Ice::IceV_InstNumbers, "instnum", | 42 clEnumValN(Ice::IceV_InstNumbers, "instnum", |
| 43 "Print instruction numbers"), | 43 "Print instruction numbers"), |
| 44 clEnumValN(Ice::IceV_Preds, "pred", "Show predecessors"), | 44 clEnumValN(Ice::IceV_Preds, "pred", "Show predecessors"), |
| 45 clEnumValN(Ice::IceV_Succs, "succ", "Show successors"), | 45 clEnumValN(Ice::IceV_Succs, "succ", "Show successors"), |
| 46 clEnumValN(Ice::IceV_Liveness, "live", "Liveness information"), | 46 clEnumValN(Ice::IceV_Liveness, "live", "Liveness information"), |
| 47 clEnumValN(Ice::IceV_RegManager, "rmgr", "Register manager status"), | |
| 48 clEnumValN(Ice::IceV_RegOrigins, "orig", "Physical register origins"), | 47 clEnumValN(Ice::IceV_RegOrigins, "orig", "Physical register origins"), |
| 49 clEnumValN(Ice::IceV_LinearScan, "regalloc", "Linear scan details"), | 48 clEnumValN(Ice::IceV_LinearScan, "regalloc", "Linear scan details"), |
| 50 clEnumValN(Ice::IceV_Frame, "frame", "Stack frame layout details"), | 49 clEnumValN(Ice::IceV_Frame, "frame", "Stack frame layout details"), |
| 51 clEnumValN(Ice::IceV_AddrOpt, "addropt", "Address mode optimization"), | 50 clEnumValN(Ice::IceV_AddrOpt, "addropt", "Address mode optimization"), |
| 52 clEnumValN(Ice::IceV_Random, "random", "Randomization details"), | 51 clEnumValN(Ice::IceV_Random, "random", "Randomization details"), |
| 53 clEnumValN(Ice::IceV_All, "all", "Use all verbose options"), | 52 clEnumValN(Ice::IceV_All, "all", "Use all verbose options"), |
| 54 clEnumValN(Ice::IceV_Most, "most", | 53 clEnumValN(Ice::IceV_Most, "most", |
| 55 "Use all verbose options except 'regalloc' and 'time'"), | 54 "Use all verbose options except 'regalloc' and 'time'"), |
| 56 clEnumValN(Ice::IceV_None, "none", "No verbosity"), clEnumValEnd)); | 55 clEnumValN(Ice::IceV_None, "none", "No verbosity"), clEnumValEnd)); |
| 57 static cl::opt<Ice::TargetArch> TargetArch( | 56 static cl::opt<Ice::TargetArch> TargetArch( |
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| 386 if (SubzeroTimingEnabled) | 385 if (SubzeroTimingEnabled) |
| 387 Ctx.dumpTimers(); | 386 Ctx.dumpTimers(); |
| 388 if (TimeEachFunction) { | 387 if (TimeEachFunction) { |
| 389 const bool DumpCumulative = false; | 388 const bool DumpCumulative = false; |
| 390 Ctx.dumpTimers(Ice::GlobalContext::TSK_Funcs, DumpCumulative); | 389 Ctx.dumpTimers(Ice::GlobalContext::TSK_Funcs, DumpCumulative); |
| 391 } | 390 } |
| 392 const bool FinalStats = true; | 391 const bool FinalStats = true; |
| 393 Ctx.dumpStats("_FINAL_", FinalStats); | 392 Ctx.dumpStats("_FINAL_", FinalStats); |
| 394 return GetReturnValue(ErrorStatus); | 393 return GetReturnValue(ErrorStatus); |
| 395 } | 394 } |
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