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Side by Side Diff: src/assembler_ia32.h

Issue 828873002: Subzero: Start writing out some relocation sections (text) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: review fixes Created 5 years, 11 months ago
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1 //===- subzero/src/assembler_ia32.h - Assembler for x86-32 ------*- C++ -*-===// 1 //===- subzero/src/assembler_ia32.h - Assembler for x86-32 ------*- C++ -*-===//
2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
3 // for details. All rights reserved. Use of this source code is governed by a 3 // for details. All rights reserved. Use of this source code is governed by a
4 // BSD-style license that can be found in the LICENSE file. 4 // BSD-style license that can be found in the LICENSE file.
5 // 5 //
6 // Modified by the Subzero authors. 6 // Modified by the Subzero authors.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // The Subzero Code Generator 10 // The Subzero Code Generator
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25 #include "IceDefs.h" 25 #include "IceDefs.h"
26 #include "IceOperand.h" 26 #include "IceOperand.h"
27 #include "IceRegistersX8632.h" 27 #include "IceRegistersX8632.h"
28 #include "IceTypes.h" 28 #include "IceTypes.h"
29 #include "IceUtils.h" 29 #include "IceUtils.h"
30 30
31 #include "assembler.h" 31 #include "assembler.h"
32 32
33 namespace Ice { 33 namespace Ice {
34 34
35 class Assembler;
36
37 using RegX8632::GPRRegister; 35 using RegX8632::GPRRegister;
38 using RegX8632::XmmRegister; 36 using RegX8632::XmmRegister;
39 using RegX8632::ByteRegister; 37 using RegX8632::ByteRegister;
40 using RegX8632::X87STRegister; 38 using RegX8632::X87STRegister;
41 39
42 namespace x86 { 40 namespace x86 {
43 41
44 const int MAX_NOP_SIZE = 8; 42 const int MAX_NOP_SIZE = 8;
45 43
46 enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 }; 44 enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 };
47 45
48 class DisplacementRelocation : public AssemblerFixup {
49 DisplacementRelocation(const DisplacementRelocation &) = delete;
50 DisplacementRelocation &operator=(const DisplacementRelocation &) = delete;
51
52 public:
53 static DisplacementRelocation *create(Assembler *Asm, FixupKind Kind,
54 const Constant *Sym) {
55 return new (Asm->Allocate<DisplacementRelocation>())
56 DisplacementRelocation(Kind, Sym);
57 }
58
59 private:
60 DisplacementRelocation(FixupKind Kind, const Constant *Sym)
61 : AssemblerFixup(Kind, Sym) {}
62 };
63
64 class Immediate { 46 class Immediate {
65 Immediate(const Immediate &) = delete; 47 Immediate(const Immediate &) = delete;
66 Immediate &operator=(const Immediate &) = delete; 48 Immediate &operator=(const Immediate &) = delete;
67 49
68 public: 50 public:
69 explicit Immediate(int32_t value) : value_(value), fixup_(nullptr) {} 51 explicit Immediate(int32_t value) : value_(value), fixup_(nullptr) {}
70 52
71 Immediate(RelocOffsetT offset, AssemblerFixup *fixup) 53 Immediate(RelocOffsetT offset, AssemblerFixup *fixup)
72 : value_(offset), fixup_(fixup) { 54 : value_(offset), fixup_(fixup) {
73 // Use the Offset in the "value" for now. If the symbol is part of 55 // Use the Offset in the "value" for now. If we decide to process fixups,
74 // ".bss", then the relocation's symbol will be plain ".bss" and 56 // we'll need to patch that offset with the true value.
75 // the value will need to be adjusted further to be sym's
76 // bss offset + Offset.
77 } 57 }
78 58
79 int32_t value() const { return value_; } 59 int32_t value() const { return value_; }
80 AssemblerFixup *fixup() const { return fixup_; } 60 AssemblerFixup *fixup() const { return fixup_; }
81 61
82 bool is_int8() const { 62 bool is_int8() const {
83 // We currently only allow 32-bit fixups, and they usually have value = 0, 63 // We currently only allow 32-bit fixups, and they usually have value = 0,
84 // so if fixup_ != nullptr, it shouldn't be classified as int8/16. 64 // so if fixup_ != nullptr, it shouldn't be classified as int8/16.
85 return fixup_ == nullptr && Utils::IsInt(8, value_); 65 return fixup_ == nullptr && Utils::IsInt(8, value_);
86 } 66 }
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246 static Address Absolute(const uintptr_t addr) { 226 static Address Absolute(const uintptr_t addr) {
247 Address result; 227 Address result;
248 result.SetModRM(0, RegX8632::Encoded_Reg_ebp); 228 result.SetModRM(0, RegX8632::Encoded_Reg_ebp);
249 result.SetDisp32(addr); 229 result.SetDisp32(addr);
250 return result; 230 return result;
251 } 231 }
252 232
253 static Address Absolute(RelocOffsetT Offset, AssemblerFixup *fixup) { 233 static Address Absolute(RelocOffsetT Offset, AssemblerFixup *fixup) {
254 Address result; 234 Address result;
255 result.SetModRM(0, RegX8632::Encoded_Reg_ebp); 235 result.SetModRM(0, RegX8632::Encoded_Reg_ebp);
256 // Use the Offset in the displacement for now. If the symbol is part of 236 // Use the Offset in the displacement for now. If we decide to process
257 // ".bss", then the relocation's symbol will be plain .bss and the 237 // fixups later, we'll need to patch up the emitted displacement.
258 // displacement will need to be adjusted further to be sym's
259 // bss offset + Offset.
260 result.SetDisp32(Offset); 238 result.SetDisp32(Offset);
261 result.SetFixup(fixup); 239 result.SetFixup(fixup);
262 return result; 240 return result;
263 } 241 }
264 242
265 static Address ofConstPool(Assembler *Asm, const Constant *Imm); 243 static Address ofConstPool(Assembler *Asm, const Constant *Imm);
266 244
267 private: 245 private:
268 Address() {} // Needed by Address::Absolute. 246 Address() {} // Needed by Address::Absolute.
269 }; 247 };
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374 llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override { 352 llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override {
375 static const uint8_t Padding[] = {0xF4}; 353 static const uint8_t Padding[] = {0xF4};
376 return llvm::ArrayRef<uint8_t>(Padding, 1); 354 return llvm::ArrayRef<uint8_t>(Padding, 1);
377 } 355 }
378 356
379 Label *GetOrCreateCfgNodeLabel(SizeT NodeNumber); 357 Label *GetOrCreateCfgNodeLabel(SizeT NodeNumber);
380 void BindCfgNodeLabel(SizeT NodeNumber) override; 358 void BindCfgNodeLabel(SizeT NodeNumber) override;
381 Label *GetOrCreateLocalLabel(SizeT Number); 359 Label *GetOrCreateLocalLabel(SizeT Number);
382 void BindLocalLabel(SizeT Number); 360 void BindLocalLabel(SizeT Number);
383 361
362 bool fixupIsPCRel(FixupKind Kind) const override {
363 // Currently assuming this is the only PC-rel relocation type used.
364 return Kind == llvm::ELF::R_386_PC32;
365 }
366
384 // Operations to emit GPR instructions (and dispatch on operand type). 367 // Operations to emit GPR instructions (and dispatch on operand type).
385 typedef void (AssemblerX86::*TypedEmitGPR)(Type, GPRRegister); 368 typedef void (AssemblerX86::*TypedEmitGPR)(Type, GPRRegister);
386 typedef void (AssemblerX86::*TypedEmitAddr)(Type, const Address &); 369 typedef void (AssemblerX86::*TypedEmitAddr)(Type, const Address &);
387 struct GPREmitterOneOp { 370 struct GPREmitterOneOp {
388 TypedEmitGPR Reg; 371 TypedEmitGPR Reg;
389 TypedEmitAddr Addr; 372 TypedEmitAddr Addr;
390 }; 373 };
391 374
392 typedef void (AssemblerX86::*TypedEmitGPRGPR)(Type, GPRRegister, GPRRegister); 375 typedef void (AssemblerX86::*TypedEmitGPRGPR)(Type, GPRRegister, GPRRegister);
393 typedef void (AssemblerX86::*TypedEmitGPRAddr)(Type, GPRRegister, 376 typedef void (AssemblerX86::*TypedEmitGPRAddr)(Type, GPRRegister,
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883 inline void AssemblerX86::EmitFixup(AssemblerFixup *fixup) { 866 inline void AssemblerX86::EmitFixup(AssemblerFixup *fixup) {
884 buffer_.EmitFixup(fixup); 867 buffer_.EmitFixup(fixup);
885 } 868 }
886 869
887 inline void AssemblerX86::EmitOperandSizeOverride() { EmitUint8(0x66); } 870 inline void AssemblerX86::EmitOperandSizeOverride() { EmitUint8(0x66); }
888 871
889 } // end of namespace x86 872 } // end of namespace x86
890 } // end of namespace Ice 873 } // end of namespace Ice
891 874
892 #endif // SUBZERO_SRC_ASSEMBLER_IA32_H_ 875 #endif // SUBZERO_SRC_ASSEMBLER_IA32_H_
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