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Side by Side Diff: dart/runtime/vm/flow_graph_compiler_arm.cc

Issue 828433005: Version 1.8.4 (Closed) Base URL: http://dart.googlecode.com/svn/branches/1.8/
Patch Set: Created 5 years, 11 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/flow_graph_compiler.h" 8 #include "vm/flow_graph_compiler.h"
9 9
10 #include "vm/ast_printer.h" 10 #include "vm/ast_printer.h"
(...skipping 1671 matching lines...) Expand 10 before | Expand all | Expand 10 after
1682 } else if (source.IsRegister() && destination.IsStackSlot()) { 1682 } else if (source.IsRegister() && destination.IsStackSlot()) {
1683 Exchange(source.reg(), 1683 Exchange(source.reg(),
1684 destination.base_reg(), destination.ToStackSlotOffset()); 1684 destination.base_reg(), destination.ToStackSlotOffset());
1685 } else if (source.IsStackSlot() && destination.IsRegister()) { 1685 } else if (source.IsStackSlot() && destination.IsRegister()) {
1686 Exchange(destination.reg(), 1686 Exchange(destination.reg(),
1687 source.base_reg(), source.ToStackSlotOffset()); 1687 source.base_reg(), source.ToStackSlotOffset());
1688 } else if (source.IsStackSlot() && destination.IsStackSlot()) { 1688 } else if (source.IsStackSlot() && destination.IsStackSlot()) {
1689 Exchange(source.base_reg(), source.ToStackSlotOffset(), 1689 Exchange(source.base_reg(), source.ToStackSlotOffset(),
1690 destination.base_reg(), destination.ToStackSlotOffset()); 1690 destination.base_reg(), destination.ToStackSlotOffset());
1691 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { 1691 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
1692 const DRegister dst = EvenDRegisterOf(destination.fpu_reg()); 1692 if (TargetCPUFeatures::neon_supported()) {
1693 DRegister src = EvenDRegisterOf(source.fpu_reg()); 1693 const QRegister dst = destination.fpu_reg();
1694 __ vmovd(DTMP, src); 1694 const QRegister src = source.fpu_reg();
1695 __ vmovd(src, dst); 1695 __ vmovq(QTMP, src);
1696 __ vmovd(dst, DTMP); 1696 __ vmovq(src, dst);
1697 __ vmovq(dst, QTMP);
1698 } else {
1699 const DRegister dst = EvenDRegisterOf(destination.fpu_reg());
1700 const DRegister src = EvenDRegisterOf(source.fpu_reg());
1701 __ vmovd(DTMP, src);
1702 __ vmovd(src, dst);
1703 __ vmovd(dst, DTMP);
1704 }
1697 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { 1705 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
1698 ASSERT(destination.IsDoubleStackSlot() || 1706 ASSERT(destination.IsDoubleStackSlot() ||
1699 destination.IsQuadStackSlot() || 1707 destination.IsQuadStackSlot() ||
1700 source.IsDoubleStackSlot() || 1708 source.IsDoubleStackSlot() ||
1701 source.IsQuadStackSlot()); 1709 source.IsQuadStackSlot());
1702 bool double_width = destination.IsDoubleStackSlot() || 1710 bool double_width = destination.IsDoubleStackSlot() ||
1703 source.IsDoubleStackSlot(); 1711 source.IsDoubleStackSlot();
1704 QRegister qreg = source.IsFpuRegister() ? source.fpu_reg() 1712 QRegister qreg = source.IsFpuRegister() ? source.fpu_reg()
1705 : destination.fpu_reg(); 1713 : destination.fpu_reg();
1706 DRegister reg = EvenDRegisterOf(qreg); 1714 DRegister reg = EvenDRegisterOf(qreg);
(...skipping 124 matching lines...) Expand 10 before | Expand all | Expand 10 after
1831 DRegister dreg = EvenDRegisterOf(reg); 1839 DRegister dreg = EvenDRegisterOf(reg);
1832 __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex)); 1840 __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex));
1833 } 1841 }
1834 1842
1835 1843
1836 #undef __ 1844 #undef __
1837 1845
1838 } // namespace dart 1846 } // namespace dart
1839 1847
1840 #endif // defined TARGET_ARCH_ARM 1848 #endif // defined TARGET_ARCH_ARM
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