Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(72)

Side by Side Diff: runtime/vm/flow_graph_compiler_mips.cc

Issue 817593002: Improve generated MIPS code for conditional expressions and branches by delaying (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
« no previous file with comments | « runtime/vm/disassembler_mips.cc ('k') | runtime/vm/intermediate_language_mips.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS.
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/flow_graph_compiler.h" 8 #include "vm/flow_graph_compiler.h"
9 9
10 #include "vm/ast_printer.h" 10 #include "vm/ast_printer.h"
(...skipping 1377 matching lines...) Expand 10 before | Expand all | Expand 10 after
1388 __ Drop(argument_count); 1388 __ Drop(argument_count);
1389 } 1389 }
1390 1390
1391 1391
1392 Condition FlowGraphCompiler::EmitEqualityRegConstCompare( 1392 Condition FlowGraphCompiler::EmitEqualityRegConstCompare(
1393 Register reg, 1393 Register reg,
1394 const Object& obj, 1394 const Object& obj,
1395 bool needs_number_check, 1395 bool needs_number_check,
1396 intptr_t token_pos) { 1396 intptr_t token_pos) {
1397 __ TraceSimMsg("EqualityRegConstCompare"); 1397 __ TraceSimMsg("EqualityRegConstCompare");
1398 ASSERT(!needs_number_check ||
1399 (!obj.IsMint() && !obj.IsDouble() && !obj.IsBigint()));
1398 if (needs_number_check) { 1400 if (needs_number_check) {
1399 StubCode* stub_code = isolate()->stub_code(); 1401 StubCode* stub_code = isolate()->stub_code();
1400 ASSERT(!obj.IsMint() && !obj.IsDouble() && !obj.IsBigint()); 1402 ASSERT(!obj.IsMint() && !obj.IsDouble() && !obj.IsBigint());
1401 __ addiu(SP, SP, Immediate(-2 * kWordSize)); 1403 __ addiu(SP, SP, Immediate(-2 * kWordSize));
1402 __ sw(reg, Address(SP, 1 * kWordSize)); 1404 __ sw(reg, Address(SP, 1 * kWordSize));
1403 __ LoadObject(TMP, obj); 1405 __ LoadObject(TMP, obj);
1404 __ sw(TMP, Address(SP, 0 * kWordSize)); 1406 __ sw(TMP, Address(SP, 0 * kWordSize));
1405 if (is_optimizing()) { 1407 if (is_optimizing()) {
1406 __ BranchLinkPatchable( 1408 __ BranchLinkPatchable(
1407 &stub_code->OptimizedIdenticalWithNumberCheckLabel()); 1409 &stub_code->OptimizedIdenticalWithNumberCheckLabel());
1408 } else { 1410 } else {
1409 __ BranchLinkPatchable( 1411 __ BranchLinkPatchable(
1410 &stub_code->UnoptimizedIdenticalWithNumberCheckLabel()); 1412 &stub_code->UnoptimizedIdenticalWithNumberCheckLabel());
1411 } 1413 }
1412 if (token_pos != Scanner::kNoSourcePos) { 1414 if (token_pos != Scanner::kNoSourcePos) {
1413 AddCurrentDescriptor(RawPcDescriptors::kRuntimeCall, 1415 AddCurrentDescriptor(RawPcDescriptors::kRuntimeCall,
1414 Isolate::kNoDeoptId, 1416 Isolate::kNoDeoptId,
1415 token_pos); 1417 token_pos);
1416 } 1418 }
1417 __ TraceSimMsg("EqualityRegConstCompare return"); 1419 __ TraceSimMsg("EqualityRegConstCompare return");
1418 // Stub returns result in CMPRES1 (if it is 0, then reg and obj are 1420 // Stub returns result in CMPRES1 (if it is 0, then reg and obj are equal).
1419 // equal) and always sets CMPRES2 to 0.
1420 __ lw(reg, Address(SP, 1 * kWordSize)); // Restore 'reg'. 1421 __ lw(reg, Address(SP, 1 * kWordSize)); // Restore 'reg'.
1421 __ addiu(SP, SP, Immediate(2 * kWordSize)); // Discard constant. 1422 __ addiu(SP, SP, Immediate(2 * kWordSize)); // Discard constant.
1423 return Condition(CMPRES1, ZR, EQ);
1422 } else { 1424 } else {
1423 __ CompareObject(CMPRES1, CMPRES2, reg, obj); 1425 int16_t imm = 0;
1426 const Register obj_reg = __ LoadConditionOperand(CMPRES1, obj, &imm);
1427 return Condition(reg, obj_reg, EQ, imm);
1424 } 1428 }
1425 return EQ;
1426 } 1429 }
1427 1430
1428 1431
1429 Condition FlowGraphCompiler::EmitEqualityRegRegCompare(Register left, 1432 Condition FlowGraphCompiler::EmitEqualityRegRegCompare(Register left,
1430 Register right, 1433 Register right,
1431 bool needs_number_check, 1434 bool needs_number_check,
1432 intptr_t token_pos) { 1435 intptr_t token_pos) {
1433 __ TraceSimMsg("EqualityRegRegCompare"); 1436 __ TraceSimMsg("EqualityRegRegCompare");
1434 __ Comment("EqualityRegRegCompare"); 1437 __ Comment("EqualityRegRegCompare");
1435 if (needs_number_check) { 1438 if (needs_number_check) {
(...skipping 15 matching lines...) Expand all
1451 } 1454 }
1452 #if defined(DEBUG) 1455 #if defined(DEBUG)
1453 if (!is_optimizing()) { 1456 if (!is_optimizing()) {
1454 // Do this *after* adding the pc descriptor! 1457 // Do this *after* adding the pc descriptor!
1455 __ LoadImmediate(S4, kInvalidObjectPointer); 1458 __ LoadImmediate(S4, kInvalidObjectPointer);
1456 __ LoadImmediate(S5, kInvalidObjectPointer); 1459 __ LoadImmediate(S5, kInvalidObjectPointer);
1457 } 1460 }
1458 #endif 1461 #endif
1459 __ TraceSimMsg("EqualityRegRegCompare return"); 1462 __ TraceSimMsg("EqualityRegRegCompare return");
1460 // Stub returns result in CMPRES1 (if it is 0, then left and right are 1463 // Stub returns result in CMPRES1 (if it is 0, then left and right are
1461 // equal) and always sets CMPRES2 to 0. 1464 // equal).
1462 __ lw(right, Address(SP, 0 * kWordSize)); 1465 __ lw(right, Address(SP, 0 * kWordSize));
1463 __ lw(left, Address(SP, 1 * kWordSize)); 1466 __ lw(left, Address(SP, 1 * kWordSize));
1464 __ addiu(SP, SP, Immediate(2 * kWordSize)); 1467 __ addiu(SP, SP, Immediate(2 * kWordSize));
1468 return Condition(CMPRES1, ZR, EQ);
1465 } else { 1469 } else {
1466 __ slt(CMPRES1, left, right); 1470 return Condition(left, right, EQ);
1467 __ slt(CMPRES2, right, left);
1468 } 1471 }
1469 return EQ;
1470 } 1472 }
1471 1473
1472 1474
1473 // This function must be in sync with FlowGraphCompiler::RecordSafepoint and 1475 // This function must be in sync with FlowGraphCompiler::RecordSafepoint and
1474 // FlowGraphCompiler::SlowPathEnvironmentFor. 1476 // FlowGraphCompiler::SlowPathEnvironmentFor.
1475 void FlowGraphCompiler::SaveLiveRegisters(LocationSummary* locs) { 1477 void FlowGraphCompiler::SaveLiveRegisters(LocationSummary* locs) {
1476 #if defined(DEBUG) 1478 #if defined(DEBUG)
1477 locs->CheckWritableInputs(); 1479 locs->CheckWritableInputs();
1478 ClobberDeadTempRegisters(locs); 1480 ClobberDeadTempRegisters(locs);
1479 #endif 1481 #endif
(...skipping 381 matching lines...) Expand 10 before | Expand all | Expand 10 after
1861 __ AddImmediate(SP, kDoubleSize); 1863 __ AddImmediate(SP, kDoubleSize);
1862 } 1864 }
1863 1865
1864 1866
1865 #undef __ 1867 #undef __
1866 1868
1867 1869
1868 } // namespace dart 1870 } // namespace dart
1869 1871
1870 #endif // defined TARGET_ARCH_MIPS 1872 #endif // defined TARGET_ARCH_MIPS
OLDNEW
« no previous file with comments | « runtime/vm/disassembler_mips.cc ('k') | runtime/vm/intermediate_language_mips.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698