Improve generated MIPS code for conditional expressions and branches by delaying

runtime/vm/constants_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_MIPS_H_
 #define VM_CONSTANTS_MIPS_H_
 
 #include "platform/assert.h"
+#include "vm/allocation.h"
+#include "vm/bitfield.h"
 
 namespace dart {
 
 enum Register {
   R0  =  0,
   R1  =  1,
   kFirstFreeCpuRegister = 2,
   R2  =  2,
   R3  =  3,
   R4  =  4,
@@ skipping 19 matching lines @@
   R23 = 23,
   R24 = 24,
   R25 = 25,
   R26 = 26,
   R27 = 27,
   R28 = 28,
   R29 = 29,
   R30 = 30,
   R31 = 31,
   kNumberOfCpuRegisters = 32,
+  IMM = 32,  // Positive value is easier to encode than kNoRegister in bitfield.
   kNoRegister = -1,
 
   // Register aliases.
   ZR = R0,
   AT = R1,
 
   V0 = R2,
   V1 = R3,
 
   A0 = R4,
@@ skipping 171 matching lines @@
 const int kDartVolatileCpuRegCount = 14;
 const Register kDartFirstVolatileCpuReg = R2;
 const Register kDartLastVolatileCpuReg = R15;
 
 // FPU registers 0 - 19 are not preserved across calls.
 const FRegister kDartFirstVolatileFpuReg = F0;
 const FRegister kDartLastVolatileFpuReg = F19;
 const int kDartVolatileFpuRegCount = 20;
 
 
-// Values for the condition field.
-// There is no condition field on MIPS, but Conditions are used and passed
-// around by the intermediate language, so we need them here, too.
-enum Condition {
+// Values for the condition field in the status register.
+// There is no dedicated status register on MIPS, but Condition values are used
+// and passed around by the intermediate language, so we need them here, too.
+// We delay code generation of a comparison that would result in a traditional
+// condition code in the status register by keeping both register operands and
+// the relational operator between them as the Condition.
+enum RelationOperator {
+  AL,  // always
+  NV,  // never
   EQ,  // equal
   NE,  // not equal
   GT,  // greater than
   GE,  // greater equal
   LT,  // less than
   LE,  // less equal
-  VS,  // overflow
+  UGT,  // unsigned greater than
+  UGE,  // unsigned greater equal
+  ULT,  // unsigned less than
+  ULE,  // unsigned less equal
+};
+
+
+class Condition : public ValueObject {

[zra, 2014/12/19 17:49:47]

Should this go in assembler_mips.h?

[regis, 2014/12/22 20:17:34]

Done.

+ public:
+  enum Bits {
+    kLeftPos = 0,
+    kLeftSize = 6,
+    kRightPos = kLeftPos + kLeftSize,
+    kRightSize = 6,
+    kRelOpPos = kRightPos + kRightSize,
+    kRelOpSize = 4,
+    kImmPos = kRelOpPos + kRelOpSize,
+    kImmSize = 16,
+  };
+
+  class LeftBits : public BitField<Register, kLeftPos, kLeftSize> {};
+  class RightBits : public BitField<Register, kRightPos, kRightSize> {};
+  class RelOpBits : public BitField<RelationOperator, kRelOpPos, kRelOpSize> {};
+  class ImmBits : public BitField<uint16_t, kImmPos, kImmSize> {};
+
+  Register left() const { return LeftBits::decode(bits_); }
+  Register right() const { return RightBits::decode(bits_); }
+  RelationOperator rel_op() const { return RelOpBits::decode(bits_); }
+  int16_t imm() const { return static_cast<int16_t>(ImmBits::decode(bits_)); }
+
+  static bool IsValidImm(int32_t value) {
+    // We want both value and value + 1 to fit in an int16_t.
+    return (-0x08000 <= value) && (value < 0x7fff);
+  }
+
+  void set_rel_op(RelationOperator value) {
+    ASSERT(IsValidRelOp(value));
+    bits_ = RelOpBits::update(value, bits_);
+  }
+
+  // Uninitialized condition.
+  Condition() : ValueObject(), bits_(0) { }
+
+  // Copy constructor.
+  Condition(const Condition& other) : ValueObject(), bits_(other.bits_) { }
+
+  // Copy assignment operator.
+  Condition& operator=(const Condition& other) {
+    bits_ = other.bits_;
+    return *this;
+  }
+
+  Condition(Register left,
+            Register right,
+            RelationOperator rel_op,
+            int16_t imm = 0) {
+    // At most one constant, ZR or immediate.
+    ASSERT(!(((left == ZR) || (left == IMM)) &&
+             ((right == ZR) || (right == IMM))));
+    // Non-zero immediate value is only allowed for IMM.
+    ASSERT((imm != 0) == ((left == IMM) || (right == IMM)));
+    set_left(left);
+    set_right(right);
+    set_rel_op(rel_op);
+    set_imm(imm);
+  }
+
+ private:
+  static bool IsValidRelOp(RelationOperator value) {
+    return (AL <= value) && (value <= ULE);
+  }
+
+  static bool IsValidRegister(Register value) {
+    return (ZR <= value) && (value <= IMM) && (value != AT);
+  }
+
+  void set_left(Register value) {
+    ASSERT(IsValidRegister(value));
+    bits_ = LeftBits::update(value, bits_);
+  }
+
+  void set_right(Register value) {
+    ASSERT(IsValidRegister(value));
+    bits_ = RightBits::update(value, bits_);
+  }
+
+  void set_imm(int16_t value) {
+    ASSERT(IsValidImm(value));
+    bits_ = ImmBits::update(static_cast<uint16_t>(value), bits_);
+  }
+
+  uword bits_;
 };
 
 
 // Constants used for the decoding or encoding of the individual fields of
 // instructions. Based on the "Table 4.25 CPU Instruction Format Fields".
 enum InstructionFields {
   kOpcodeShift = 26,
   kOpcodeBits = 6,
   kRsShift = 21,
   kRsBits = 5,
@@ skipping 94 matching lines @@
   SLLV = 4,
   SRLV = 6,
   SRAV = 7,
   JR = 8,
   JALR = 9,
   MOVZ = 10,
   MOVN = 11,
   SYSCALL = 12,
   BREAK = 13,
   SYNC = 15,
-  MFHI =16,
+  MFHI = 16,
   MTHI = 17,
   MFLO = 18,
   MTLO = 19,
   MULT = 24,
   MULTU = 25,
   DIV = 26,
   DIVU = 27,
   ADD = 32,
   ADDU = 33,
   SUB = 34,
@@ skipping 258 matching lines @@
 #endif  // defined(DEBUG)
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_MIPS_H_