Improve generated MIPS code for conditional expressions and branches by delaying

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 916 matching lines @@
     }
 
     if (Utils::IsUint(kImmBits, imm)) {
       andi(rd, rs, Immediate(imm));
     } else {
       LoadImmediate(TMP, imm);
       and_(rd, rs, TMP);
     }
   }
 
+  void OrImmediate(Register rd, Register rs, int32_t imm) {
+    ASSERT(!in_delay_slot_);
+    if (imm == 0) {
+      mov(rd, rs);
+      return;
+    }
+
+    if (Utils::IsUint(kImmBits, imm)) {
+      ori(rd, rs, Immediate(imm));
+    } else {
+      LoadImmediate(TMP, imm);
+      or_(rd, rs, TMP);
+    }
+  }
+
+  void XorImmediate(Register rd, Register rs, int32_t imm) {
+    ASSERT(!in_delay_slot_);
+    if (imm == 0) {
+      mov(rd, rs);
+      return;
+    }
+
+    if (Utils::IsUint(kImmBits, imm)) {
+      xori(rd, rs, Immediate(imm));
+    } else {
+      LoadImmediate(TMP, imm);
+      xor_(rd, rs, TMP);
+    }
+  }
+
+  // Branch to label if condition is true.
+  void BranchOnCondition(Condition cond, Label* l) {
+    ASSERT(!in_delay_slot_);
+    Register left = cond.left();
+    Register right = cond.right();
+    RelationOperator rel_op = cond.rel_op();
+    switch (rel_op) {
+      case NV: return;
+      case AL: b(l); return;
+      case EQ:  // fall through.
+      case NE: {
+        if (left == IMM) {
+          addiu(AT, ZR, Immediate(cond.imm()));

[zra, 2014/12/19 17:49:47]

Why not LoadImmediate?

[regis, 2014/12/22 20:17:34]

I like to see exactly what instruction we generate. But more importantly, I do
not want to load a value that would not fit in a 16-bit immediate field.

+          left = AT;
+        } else if (right == IMM) {
+          addiu(AT, ZR, Immediate(cond.imm()));
+          right = AT;
+        }
+        if (rel_op == EQ) {
+          beq(left, right, l);
+        } else {
+          bne(left, right, l);
+        }
+        break;
+      }
+      case GT: {
+        if (left == ZR) {
+          bltz(right, l);
+        } else if (right == ZR) {
+          bgtz(left, l);
+        } else if (left == IMM) {
+          slti(AT, right, Immediate(cond.imm()));
+          bne(AT, ZR, l);
+        } else if (right == IMM) {
+          slti(AT, left, Immediate(cond.imm() + 1));
+          beq(AT, ZR, l);
+        } else {
+          slt(AT, right, left);
+          bne(AT, ZR, l);
+        }
+        break;
+      }
+      case GE: {
+        if (left == ZR) {
+          blez(right, l);
+        } else if (right == ZR) {
+          bgez(left, l);
+        } else if (left == IMM) {
+          slti(AT, right, Immediate(cond.imm() + 1));
+          bne(AT, ZR, l);
+        } else if (right == IMM) {
+          slti(AT, left, Immediate(cond.imm()));
+          beq(AT, ZR, l);
+        } else {
+          slt(AT, left, right);
+          beq(AT, ZR, l);
+        }
+        break;
+      }
+      case LT: {
+        if (left == ZR) {
+          bgtz(right, l);
+        } else if (right == ZR) {
+          bltz(left, l);
+        } else if (left == IMM) {
+          slti(AT, right, Immediate(cond.imm() + 1));
+          beq(AT, ZR, l);
+        } else if (right == IMM) {
+          slti(AT, left, Immediate(cond.imm()));
+          bne(AT, ZR, l);
+        } else {
+          slt(AT, left, right);
+          bne(AT, ZR, l);
+        }
+        break;
+      }
+      case LE: {
+        if (left == ZR) {
+          bgez(right, l);
+        } else if (right == ZR) {
+          blez(left, l);
+        } else if (left == IMM) {
+          slti(AT, right, Immediate(cond.imm()));
+          beq(AT, ZR, l);
+        } else if (right == IMM) {
+          slti(AT, left, Immediate(cond.imm() + 1));
+          bne(AT, ZR, l);
+        } else {
+          slt(AT, right, left);
+          beq(AT, ZR, l);
+        }
+        break;
+      }
+      case UGT: {
+        ASSERT((left != IMM) && (right != IMM));  // No unsigned constants used.

[zra, 2014/12/19 17:49:47]

What do you do if you want to branch on an unsigned comparison with an
immediate? Does that not come up?

[regis, 2014/12/22 20:17:34]

This does not come up. The compiler will always allocate a pair of registers for
an unsigned constant.

+        if (left == ZR) {
+          // NV: Never branch. Fall through.
+        } else if (right == ZR) {
+          bne(left, ZR, l);
+        } else {
+          sltu(AT, right, left);
+          bne(AT, ZR, l);
+        }
+        break;
+      }
+      case UGE: {
+        ASSERT((left != IMM) && (right != IMM));  // No unsigned constants used.
+        if (left == ZR) {
+          beq(right, ZR, l);
+        } else if (right == ZR) {
+          // AL: Always branch to l.
+          beq(ZR, ZR, l);
+        } else {
+          sltu(AT, left, right);
+          beq(AT, ZR, l);
+        }
+        break;
+      }
+      case ULT: {
+        ASSERT((left != IMM) && (right != IMM));  // No unsigned constants used.
+        if (left == ZR) {
+          bne(right, ZR, l);
+        } else if (right == ZR) {
+          // NV: Never branch. Fall through.
+        } else {
+          sltu(AT, left, right);
+          bne(AT, ZR, l);
+        }
+        break;
+      }
+      case ULE: {
+        ASSERT((left != IMM) && (right != IMM));  // No unsigned constants used.
+        if (left == ZR) {
+          // AL: Always branch to l.
+          beq(ZR, ZR, l);
+        } else if (right == ZR) {
+          beq(left, ZR, l);
+        } else {
+          sltu(AT, right, left);
+          beq(AT, ZR, l);
+        }
+        break;
+      }
+      default:
+        UNREACHABLE();
+    }
+  }
+
   void BranchEqual(Register rd, Register rn, Label* l) {
     beq(rd, rn, l);
   }
 
   void BranchEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     if (imm.value() == 0) {
       beq(rd, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
@@ skipping 35 matching lines @@
     ASSERT(!in_delay_slot_);
     slt(CMPRES2, rs, rd);  // CMPRES2 = rd > rs ? 1 : 0.
     bne(CMPRES2, ZR, l);
   }
 
   void BranchSignedGreater(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     if (imm.value() == 0) {
       bgtz(rd, l);
     } else {
-      ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, imm.value());
-      BranchSignedGreater(rd, CMPRES2, l);
+      if (Utils::IsInt(kImmBits, imm.value() + 1)) {
+        slti(CMPRES2, rd, Immediate(imm.value() + 1));
+        beq(CMPRES2, ZR, l);
+      } else {
+        ASSERT(rd != CMPRES2);
+        LoadImmediate(CMPRES2, imm.value());
+        BranchSignedGreater(rd, CMPRES2, l);
+      }
     }
   }
 
   void BranchUnsignedGreater(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     sltu(CMPRES2, rs, rd);
     bne(CMPRES2, ZR, l);
   }
 
   void BranchUnsignedGreater(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     if (imm.value() == 0) {
       BranchNotEqual(rd, Immediate(0), l);
     } else {
-      ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, imm.value());
-      BranchUnsignedGreater(rd, CMPRES2, l);
+      if ((imm.value() != -1) && Utils::IsInt(kImmBits, imm.value() + 1)) {
+        sltiu(CMPRES2, rd, Immediate(imm.value() + 1));
+        beq(CMPRES2, ZR, l);
+      } else {
+        ASSERT(rd != CMPRES2);
+        LoadImmediate(CMPRES2, imm.value());
+        BranchUnsignedGreater(rd, CMPRES2, l);
+      }
     }
   }
 
   void BranchSignedGreaterEqual(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     slt(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
     beq(CMPRES2, ZR, l);  // If CMPRES2 = 0, then rd >= rs.
   }
 
   void BranchSignedGreaterEqual(Register rd, const Immediate& imm, Label* l) {
@@ skipping 16 matching lines @@
     ASSERT(!in_delay_slot_);
     sltu(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
     beq(CMPRES2, ZR, l);
   }
 
   void BranchUnsignedGreaterEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     if (imm.value() == 0) {
       b(l);
     } else {
-      if (Utils::IsUint(kImmBits, imm.value())) {
+      if (Utils::IsInt(kImmBits, imm.value())) {
         sltiu(CMPRES2, rd, imm);
         beq(CMPRES2, ZR, l);
       } else {
         ASSERT(rd != CMPRES2);
         LoadImmediate(CMPRES2, imm.value());
         BranchUnsignedGreaterEqual(rd, CMPRES2, l);
       }
     }
   }
 
@@ skipping 18 matching lines @@
     }
   }
 
   void BranchUnsignedLess(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     BranchUnsignedGreater(rs, rd, l);
   }
 
   void BranchUnsignedLess(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    ASSERT(imm.value() != 0);
-    if (Utils::IsInt(kImmBits, imm.value())) {
-      sltiu(CMPRES2, rd, imm);
-      bne(CMPRES2, ZR, l);
+    if (imm.value() == 0) {
+      // Never branch. Fall through.
     } else {
-      ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, imm.value());
-      BranchUnsignedGreater(CMPRES2, rd, l);
+      if (Utils::IsInt(kImmBits, imm.value())) {
+        sltiu(CMPRES2, rd, imm);
+        bne(CMPRES2, ZR, l);
+      } else {
+        ASSERT(rd != CMPRES2);
+        LoadImmediate(CMPRES2, imm.value());
+        BranchUnsignedGreater(CMPRES2, rd, l);
+      }
     }
   }
 
   void BranchSignedLessEqual(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     BranchSignedGreaterEqual(rs, rd, l);
   }
 
   void BranchSignedLessEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     if (imm.value() == 0) {
       blez(rd, l);
     } else {
-      ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, imm.value());
-      BranchSignedGreaterEqual(CMPRES2, rd, l);
+      if (Utils::IsInt(kImmBits, imm.value() + 1)) {
+        slti(CMPRES2, rd, Immediate(imm.value() + 1));
+        bne(CMPRES2, ZR, l);
+      } else {
+        ASSERT(rd != CMPRES2);
+        LoadImmediate(CMPRES2, imm.value());
+        BranchSignedGreaterEqual(CMPRES2, rd, l);
+      }
     }
   }
 
   void BranchUnsignedLessEqual(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     BranchUnsignedGreaterEqual(rs, rd, l);
   }
 
   void BranchUnsignedLessEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    ASSERT(rd != CMPRES2);
-    LoadImmediate(CMPRES2, imm.value());
-    BranchUnsignedGreaterEqual(CMPRES2, rd, l);
+    if (imm.value() == 0) {
+      beq(rd, ZR, l);
+    } else {
+      if ((imm.value() != -1) && Utils::IsInt(kImmBits, imm.value() + 1)) {
+        sltiu(CMPRES2, rd, Immediate(imm.value() + 1));
+        bne(CMPRES2, ZR, l);
+      } else {
+        ASSERT(rd != CMPRES2);
+        LoadImmediate(CMPRES2, imm.value());
+        BranchUnsignedGreaterEqual(CMPRES2, rd, l);
+      }
+    }
   }
 
   void Push(Register rt) {
     ASSERT(!in_delay_slot_);
     addiu(SP, SP, Immediate(-kWordSize));
     sw(rt, Address(SP));
   }
 
   void Pop(Register rt) {
     ASSERT(!in_delay_slot_);
@@ skipping 77 matching lines @@
   // Create a frame for calling into runtime that preserves all volatile
   // registers.  Frame's SP is guaranteed to be correctly aligned and
   // frame_space bytes are reserved under it.
   void EnterCallRuntimeFrame(intptr_t frame_space);
   void LeaveCallRuntimeFrame();
 
   void LoadWordFromPoolOffset(Register rd, int32_t offset);
   void LoadObject(Register rd, const Object& object);
   void PushObject(const Object& object);
 
-  // Compares rn with the object. Returns results in rd1 and rd2.
-  // rd1 is 1 if rn < object. rd2 is 1 if object < rn. Since both cannot be
-  // 1, rd1 == rd2 (== 0) iff rn == object.
-  void CompareObject(Register rd1, Register rd2,
-                     Register rn, const Object& object);
-
   void LoadIsolate(Register result);
 
   void LoadClassId(Register result, Register object);
   void LoadClassById(Register result, Register class_id);
   void LoadClass(Register result, Register object);
   void LoadTaggedClassIdMayBeSmi(Register result, Register object);
 
   void ComputeRange(Register result,
                     Register value,
                     Label* miss);
@@ skipping 194 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_