Add code comments to inline cache stubs.

runtime/vm/stub_code_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/code_generator.h"
 #include "vm/compiler.h"
@@ skipping 1333 matching lines @@
 
 
 // Note: S5 must be preserved.
 // Attempt a quick Smi operation for known operations ('kind'). The ICData
 // must have been primed with a Smi/Smi check that will be used for counting
 // the invocations.
 static void EmitFastSmiOp(Assembler* assembler,
                           Token::Kind kind,
                           intptr_t num_args,
                           Label* not_smi_or_overflow) {
+  __ Comment("Fast Smi op");
   ASSERT(num_args == 2);
   __ lw(T0, Address(SP, 0 * kWordSize));  // Left.
   __ lw(T1, Address(SP, 1 * kWordSize));  // Right.
   __ or_(CMPRES1, T0, T1);
   __ andi(CMPRES1, CMPRES1, Immediate(kSmiTagMask));
   __ bne(CMPRES1, ZR, not_smi_or_overflow);
   switch (kind) {
     case Token::kADD: {
      __ AdduDetectOverflow(V0, T1, T0, CMPRES1);  // Add.
      __ bltz(CMPRES1, not_smi_or_overflow);  // Fall through on overflow.
@@ skipping 71 matching lines @@
     __ lw(T0, FieldAddress(S5, ICData::state_bits_offset()));
     ASSERT(ICData::NumArgsTestedShift() == 0);  // No shift needed.
     __ andi(T0, T0, Immediate(ICData::NumArgsTestedMask()));
     __ BranchEqual(T0, Immediate(num_args), &ok);
     __ Stop("Incorrect stub for IC data");
     __ Bind(&ok);
   }
 #endif  // DEBUG
 
 
-  // Check single stepping.
+  __ Comment("Check single stepping");
   Label stepping, done_stepping;
   __ LoadIsolate(T0);
   __ lbu(T0, Address(T0, Isolate::single_step_offset()));
   __ BranchNotEqual(T0, Immediate(0), &stepping);
   __ Bind(&done_stepping);
 
+  __ Comment("Range feedback collection");
   Label not_smi_or_overflow;
   if (range_collection_mode == kCollectRanges) {
     ASSERT((num_args == 1) || (num_args == 2));
     if (num_args == 2) {
       __ lw(T0, Address(SP, 1 * kWordSize));
       __ UpdateRangeFeedback(T0, 0, S5, T1, &not_smi_or_overflow);
     }
 
     __ lw(T0, Address(SP, 0 * kWordSize));
     __ UpdateRangeFeedback(T0, num_args - 1, S5, T1, &not_smi_or_overflow);
   }
   if (kind != Token::kILLEGAL) {
     EmitFastSmiOp(assembler, kind, num_args, &not_smi_or_overflow);
   }
   __ Bind(&not_smi_or_overflow);
 
+  __ Comment("Extract ICData initial values and receiver cid");
   // Load argument descriptor into S4.
   __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset()));
   // Preserve return address, since RA is needed for subroutine call.
   __ mov(T2, RA);
   // Loop that checks if there is an IC data match.
   Label loop, update, test, found;
   // S5: IC data object (preserved).
   __ lw(T0, FieldAddress(S5, ICData::ic_data_offset()));
   // T0: ic_data_array with check entries: classes and target functions.
   __ AddImmediate(T0, Array::data_offset() - kHeapObjectTag);
   // T0: points directly to the first ic data array element.
 
   // Get the receiver's class ID (first read number of arguments from
   // arguments descriptor array and then access the receiver from the stack).
   __ lw(T1, FieldAddress(S4, ArgumentsDescriptor::count_offset()));
   __ LoadImmediate(TMP, Smi::RawValue(1));
   __ subu(T1, T1, TMP);
   __ sll(T3, T1, 1);  // T1 (argument_count - 1) is smi.
   __ addu(T3, T3, SP);
   __ lw(T3, Address(T3));
   __ LoadTaggedClassIdMayBeSmi(T3, T3);
 
   // T1: argument_count - 1 (smi).
   // T3: receiver's class ID (smi).
   __ b(&test);
   __ delay_slot()->lw(T4, Address(T0));  // First class id (smi) to check.
 
+  __ Comment("ICData loop");
   __ Bind(&loop);
   for (int i = 0; i < num_args; i++) {
     if (i > 0) {
       // If not the first, load the next argument's class ID.
       __ LoadImmediate(T3, Smi::RawValue(-i));
       __ addu(T3, T1, T3);
       __ sll(T3, T3, 1);
       __ addu(T3, SP, T3);
       __ lw(T3, Address(T3));
       __ LoadTaggedClassIdMayBeSmi(T3, T3);
@@ skipping 21 matching lines @@
     __ LoadTaggedClassIdMayBeSmi(T3, T3);
   }
 
   const intptr_t entry_size = ICData::TestEntryLengthFor(num_args) * kWordSize;
   __ AddImmediate(T0, entry_size);  // Next entry.
   __ lw(T4, Address(T0));  // Next class ID.
 
   __ Bind(&test);
   __ BranchNotEqual(T4, Immediate(Smi::RawValue(kIllegalCid)), &loop);  // Done?
 
-  // IC miss.
+  __ Comment("IC miss");
   // Restore return address.
   __ mov(RA, T2);
 
   // Compute address of arguments (first read number of arguments from
   // arguments descriptor array and then compute address on the stack).
   // T1: argument_count - 1 (smi).
   __ sll(T1, T1, 1);  // T1 is Smi.
   __ addu(T1, SP, T1);
   // T1: address of receiver.
   // Create a stub frame as we are pushing some objects on the stack before
@@ skipping 23 matching lines @@
   __ lw(S5, Address(SP, (num_slots - 1) * kWordSize));
   // Remove the call arguments pushed earlier, including the IC data object
   // and the arguments descriptor array.
   __ addiu(SP, SP, Immediate(num_slots * kWordSize));
   __ LeaveStubFrame();
 
   Label call_target_function;
   __ b(&call_target_function);
 
   __ Bind(&found);
+  __ Comment("Update caller's counter");
   // T0: Pointer to an IC data check group.
   const intptr_t target_offset = ICData::TargetIndexFor(num_args) * kWordSize;
   const intptr_t count_offset = ICData::CountIndexFor(num_args) * kWordSize;
   __ lw(T3, Address(T0, target_offset));
 
   // Update counter.
   __ lw(T4, Address(T0, count_offset));
   __ AddImmediateDetectOverflow(T7, T4, Smi::RawValue(1), T5, T6);
   __ slt(CMPRES1, T5, ZR);  // T5 is < 0 if there was overflow.
   __ LoadImmediate(T4, Smi::RawValue(Smi::kMaxValue));
   __ movz(T4, T7, CMPRES1);
   __ sw(T4, Address(T0, count_offset));
 
+  __ Comment("Call target");
   __ Bind(&call_target_function);
   // T0 <- T3: Target function.
   __ mov(T0, T3);
   Label is_compiled;
   __ lw(T4, FieldAddress(T0, Function::instructions_offset()));
   __ AddImmediate(T4, Instructions::HeaderSize() - kHeapObjectTag);
   if (range_collection_mode == kCollectRanges) {
     const intptr_t frame_size = num_args + 2;
     __ lw(T3, Address(SP, 0 * kWordSize));
     if (num_args == 2) {
@@ skipping 638 matching lines @@
   const Register right = T0;
   __ lw(left, Address(SP, 1 * kWordSize));
   __ lw(right, Address(SP, 0 * kWordSize));
   GenerateIdenticalWithNumberCheckStub(assembler, left, right, temp1, temp2);
   __ Ret();
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS