Subzero: Convert NULL->nullptr.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 447 matching lines @@
 #undef X
 };
 
 Variable *TargetX8632::getPhysicalRegister(SizeT RegNum, Type Ty) {
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(RegX8632::Reg_NUM);
   assert(RegNum < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
-  if (Reg == NULL) {
+  if (Reg == nullptr) {
     Reg = Func->makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
     // Specially mark esp as an "argument" so that it is considered
     // live upon function entry.
     if (RegNum == RegX8632::Reg_esp) {
       Func->addImplicitArg(Reg);
       Reg->setIgnoreLiveness();
     }
   }
@@ skipping 564 matching lines @@
   // is still typed as I32.
   case IceType_f64:
     break;
   }
   Variable *Lo = Var->getLo();
   Variable *Hi = Var->getHi();
   if (Lo) {
     assert(Hi);
     return;
   }
-  assert(Hi == NULL);
+  assert(Hi == nullptr);
   Lo = Func->makeVariable(IceType_i32);
   Hi = Func->makeVariable(IceType_i32);
   if (ALLOW_DUMP) {
     Lo->setName(Func, Var->getName(Func) + "__lo");
     Hi->setName(Func, Var->getName(Func) + "__hi");
   }
   Var->setLoHi(Lo, Hi);
   if (Var->getIsArg()) {
     Lo->setIsArg();
     Hi->setIsArg();
@@ skipping 10 matching lines @@
   }
   if (ConstantInteger64 *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     return Ctx->getConstantInt32(static_cast<uint32_t>(Const->getValue()));
   }
   if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
     return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(),
                                    Mem->getOffset(), Mem->getIndex(),
                                    Mem->getShift(), Mem->getSegmentRegister());
   }
   llvm_unreachable("Unsupported operand type");
-  return NULL;
+  return nullptr;
 }
 
 Operand *TargetX8632::hiOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64);
   if (Operand->getType() != IceType_i64)
     return Operand;
   if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
     split64(Var);
     return Var->getHi();
   }
   if (ConstantInteger64 *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     return Ctx->getConstantInt32(
         static_cast<uint32_t>(Const->getValue() >> 32));
   }
   if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
     Constant *Offset = Mem->getOffset();
-    if (Offset == NULL) {
+    if (Offset == nullptr) {
       Offset = Ctx->getConstantInt32(4);
     } else if (ConstantInteger32 *IntOffset =
                    llvm::dyn_cast<ConstantInteger32>(Offset)) {
       Offset = Ctx->getConstantInt32(4 + IntOffset->getValue());
     } else if (ConstantRelocatable *SymOffset =
                    llvm::dyn_cast<ConstantRelocatable>(Offset)) {
       assert(!Utils::WouldOverflowAdd(SymOffset->getOffset(), 4));
       Offset =
           Ctx->getConstantSym(4 + SymOffset->getOffset(), SymOffset->getName(),
                               SymOffset->getSuppressMangling());
     }
     return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(), Offset,
                                    Mem->getIndex(), Mem->getShift(),
                                    Mem->getSegmentRegister());
   }
   llvm_unreachable("Unsupported operand type");
-  return NULL;
+  return nullptr;
 }
 
 llvm::SmallBitVector TargetX8632::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegX8632::Reg_NUM);
 
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   if (scratch && (Include & RegSet_CallerSave))                                \
     Registers[RegX8632::val] = true;                                           \
@@ skipping 66 matching lines @@
   Variable *Dest = Inst->getDest();
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   if (Dest->getType() == IceType_i64) {
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     Operand *Src1Lo = loOperand(Src1);
     Operand *Src1Hi = hiOperand(Src1);
-    Variable *T_Lo = NULL, *T_Hi = NULL;
+    Variable *T_Lo = nullptr, *T_Hi = nullptr;
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       break;
     case InstArithmetic::Add:
       _mov(T_Lo, Src0Lo);
       _add(T_Lo, Src1Lo);
       _mov(DestLo, T_Lo);
       _mov(T_Hi, Src0Hi);
       _adc(T_Hi, Src1Hi);
@@ skipping 25 matching lines @@
       break;
     case InstArithmetic::Sub:
       _mov(T_Lo, Src0Lo);
       _sub(T_Lo, Src1Lo);
       _mov(DestLo, T_Lo);
       _mov(T_Hi, Src0Hi);
       _sbb(T_Hi, Src1Hi);
       _mov(DestHi, T_Hi);
       break;
     case InstArithmetic::Mul: {
-      Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
+      Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
       Variable *T_4Lo = makeReg(IceType_i32, RegX8632::Reg_eax);
       Variable *T_4Hi = makeReg(IceType_i32, RegX8632::Reg_edx);
       // gcc does the following:
       // a=b*c ==>
       //   t1 = b.hi; t1 *=(imul) c.lo
       //   t2 = c.hi; t2 *=(imul) b.lo
       //   t3:eax = b.lo
       //   t4.hi:edx,t4.lo:eax = t3:eax *(mul) c.lo
       //   a.lo = t4.lo
       //   t4.hi += t1
@@ skipping 25 matching lines @@
       //   t3 = shld t3, t2, t1
       //   t2 = shl t2, t1
       //   test t1, 0x20
       //   je L1
       //   use(t3)
       //   t3 = t2
       //   t2 = 0
       // L1:
       //   a.lo = t2
       //   a.hi = t3
-      Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
+      Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
       Constant *BitTest = Ctx->getConstantInt32(0x20);
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
       _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shld(T_3, T_2, T_1);
       _shl(T_2, T_1);
       _test(T_1, BitTest);
       _br(CondX86::Br_e, Label);
@@ skipping 14 matching lines @@
       //   t2 = shrd t2, t3, t1
       //   t3 = shr t3, t1
       //   test t1, 0x20
       //   je L1
       //   use(t2)
       //   t2 = t3
       //   t3 = 0
       // L1:
       //   a.lo = t2
       //   a.hi = t3
-      Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
+      Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
       Constant *BitTest = Ctx->getConstantInt32(0x20);
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
       _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shrd(T_2, T_3, T_1);
       _shr(T_3, T_1);
       _test(T_1, BitTest);
       _br(CondX86::Br_e, Label);
@@ skipping 14 matching lines @@
       //   t2 = shrd t2, t3, t1
       //   t3 = sar t3, t1
       //   test t1, 0x20
       //   je L1
       //   use(t2)
       //   t2 = t3
       //   t3 = sar t3, 0x1f
       // L1:
       //   a.lo = t2
       //   a.hi = t3
-      Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
+      Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
       Constant *BitTest = Ctx->getConstantInt32(0x20);
       Constant *SignExtend = Ctx->getConstantInt32(0x1f);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
       _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shrd(T_2, T_3, T_1);
       _sar(T_3, T_1);
       _test(T_1, BitTest);
       _br(CondX86::Br_e, Label);
@@ skipping 164 matching lines @@
       Variable *T = makeReg(Dest->getType());
       _movp(T, Src0);
       _divps(T, Src1);
       _movp(Dest, T);
     } break;
     case InstArithmetic::Frem:
       scalarizeArithmetic(Inst->getOp(), Dest, Src0, Src1);
       break;
     }
   } else { // Dest->getType() is non-i64 scalar
-    Variable *T_edx = NULL;
-    Variable *T = NULL;
+    Variable *T_edx = nullptr;
+    Variable *T = nullptr;
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       break;
     case InstArithmetic::Add:
       _mov(T, Src0);
       _add(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::And:
@@ skipping 52 matching lines @@
       if (!llvm::isa<Constant>(Src1))
         Src1 = legalizeToVar(Src1, RegX8632::Reg_ecx);
       _sar(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::Udiv:
       // div and idiv are the few arithmetic operators that do not allow
       // immediates as the operand.
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
       if (isByteSizedArithType(Dest->getType())) {
-        Variable *T_ah = NULL;
+        Variable *T_ah = nullptr;
         Constant *Zero = Ctx->getConstantZero(IceType_i8);
         _mov(T, Src0, RegX8632::Reg_eax);
         _mov(T_ah, Zero, RegX8632::Reg_ah);
         _div(T, Src1, T_ah);
         _mov(Dest, T);
       } else {
         Constant *Zero = Ctx->getConstantZero(IceType_i32);
         _mov(T, Src0, RegX8632::Reg_eax);
         _mov(T_edx, Zero, RegX8632::Reg_edx);
         _div(T, Src1, T_edx);
@@ skipping 11 matching lines @@
         T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
         _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T_edx, T);
         _idiv(T, Src1, T_edx);
         _mov(Dest, T);
       }
       break;
     case InstArithmetic::Urem:
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
       if (isByteSizedArithType(Dest->getType())) {
-        Variable *T_ah = NULL;
+        Variable *T_ah = nullptr;
         Constant *Zero = Ctx->getConstantZero(IceType_i8);
         _mov(T, Src0, RegX8632::Reg_eax);
         _mov(T_ah, Zero, RegX8632::Reg_ah);
         _div(T_ah, Src1, T);
         _mov(Dest, T_ah);
       } else {
         Constant *Zero = Ctx->getConstantZero(IceType_i32);
         _mov(T_edx, Zero, RegX8632::Reg_edx);
         _mov(T, Src0, RegX8632::Reg_eax);
         _div(T_edx, Src1, T);
@@ skipping 53 matching lines @@
 void TargetX8632::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *Src0 = Inst->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
     Src0 = legalize(Src0);
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
-    Variable *T_Lo = NULL, *T_Hi = NULL;
+    Variable *T_Lo = nullptr, *T_Hi = nullptr;
     _mov(T_Lo, Src0Lo);
     _mov(DestLo, T_Lo);
     _mov(T_Hi, Src0Hi);
     _mov(DestHi, T_Hi);
   } else {
     // If Dest is in memory, then RI is either a physical register or
     // an immediate, otherwise RI can be anything.
     Operand *RI =
         legalize(Src0, Dest->hasReg() ? Legal_All : Legal_Reg | Legal_Imm);
     if (isVectorType(Dest->getType()))
@@ skipping 97 matching lines @@
     Variable *Reg = legalizeToVar(XmmArgs[i], RegX8632::Reg_xmm0 + i);
     // Generate a FakeUse of register arguments so that they do not get
     // dead code eliminated as a result of the FakeKill of scratch
     // registers after the call.
     Context.insert(InstFakeUse::create(Func, Reg));
   }
   // Generate the call instruction.  Assign its result to a temporary
   // with high register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
-  Variable *ReturnReg = NULL;
-  Variable *ReturnRegHi = NULL;
+  Variable *ReturnReg = nullptr;
+  Variable *ReturnRegHi = nullptr;
   if (Dest) {
     switch (Dest->getType()) {
     case IceType_NUM:
       llvm_unreachable("Invalid Call dest type");
       break;
     case IceType_void:
       break;
     case IceType_i1:
     case IceType_i8:
     case IceType_i16:
     case IceType_i32:
       ReturnReg = makeReg(Dest->getType(), RegX8632::Reg_eax);
       break;
     case IceType_i64:
       ReturnReg = makeReg(IceType_i32, RegX8632::Reg_eax);
       ReturnRegHi = makeReg(IceType_i32, RegX8632::Reg_edx);
       break;
     case IceType_f32:
     case IceType_f64:
-      // Leave ReturnReg==ReturnRegHi==NULL, and capture the result with
+      // Leave ReturnReg==ReturnRegHi==nullptr, and capture the result with
       // the fstp instruction.
       break;
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
       ReturnReg = makeReg(Dest->getType(), RegX8632::Reg_xmm0);
@@ skipping 103 matching lines @@
       if (Src0RM->getType() == IceType_i32) {
         _mov(T_Lo, Src0RM);
       } else if (Src0RM->getType() == IceType_i1) {
         _movzx(T_Lo, Src0RM);
         _shl(T_Lo, Shift);
         _sar(T_Lo, Shift);
       } else {
         _movsx(T_Lo, Src0RM);
       }
       _mov(DestLo, T_Lo);
-      Variable *T_Hi = NULL;
+      Variable *T_Hi = nullptr;
       _mov(T_Hi, T_Lo);
       if (Src0RM->getType() != IceType_i1)
         // For i1, the sar instruction is already done above.
         _sar(T_Hi, Shift);
       _mov(DestHi, T_Hi);
     } else if (Src0RM->getType() == IceType_i1) {
       // t1 = src
       // shl t1, dst_bitwidth - 1
       // sar t1, dst_bitwidth - 1
       // dst = t1
@@ skipping 78 matching lines @@
       Variable *T = makeReg(Dest->getType());
       _movp(T, Src0RM);
       _pand(T, OneMask);
       _movp(Dest, T);
     } else {
       Operand *Src0 = Inst->getSrc(0);
       if (Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       // t1 = trunc Src0RM; Dest = t1
-      Variable *T = NULL;
+      Variable *T = nullptr;
       _mov(T, Src0RM);
       if (Dest->getType() == IceType_i1)
         _and(T, Ctx->getConstantInt1(1));
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Fptrunc:
   case InstCast::Fpext: {
     Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
@@ skipping 175 matching lines @@
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Type DestType = Dest->getType();
       Type SrcType = Src0RM->getType();
       (void)DestType;
       assert((DestType == IceType_i32 && SrcType == IceType_f32) ||
              (DestType == IceType_f32 && SrcType == IceType_i32));
       // a.i32 = bitcast b.f32 ==>
       //   t.f32 = b.f32
       //   s.f32 = spill t.f32
       //   a.i32 = s.f32
-      Variable *T = NULL;
+      Variable *T = nullptr;
       // TODO: Should be able to force a spill setup by calling legalize() with
       // Legal_Mem and not Legal_Reg or Legal_Imm.
       SpillVariable *SpillVar = Func->makeVariable<SpillVariable>(SrcType);
       SpillVar->setLinkedTo(Dest);
       Variable *Spill = SpillVar;
       Spill->setWeight(RegWeight::Zero);
       _mov(T, Src0RM);
       _mov(Spill, T);
       _mov(Dest, Spill);
     } break;
@@ skipping 34 matching lines @@
       //   FakeDef(s.f64)
       //   lo(s.f64) = t_lo.i32
       //   t_hi.i32 = b_hi.i32
       //   hi(s.f64) = t_hi.i32
       //   a.f64 = s.f64
       SpillVariable *SpillVar = Func->makeVariable<SpillVariable>(IceType_f64);
       SpillVar->setLinkedTo(Dest);
       Variable *Spill = SpillVar;
       Spill->setWeight(RegWeight::Zero);
 
-      Variable *T_Lo = NULL, *T_Hi = NULL;
+      Variable *T_Lo = nullptr, *T_Hi = nullptr;
       VariableSplit *SpillLo =
           VariableSplit::create(Func, Spill, VariableSplit::Low);
       VariableSplit *SpillHi =
           VariableSplit::create(Func, Spill, VariableSplit::High);
       _mov(T_Lo, loOperand(Src0));
       // Technically, the Spill is defined after the _store happens, but
       // SpillLo is considered a "use" of Spill so define Spill before it
       // is used.
       Context.insert(InstFakeDef::create(Func, Spill));
       _store(T_Lo, SpillLo);
@@ skipping 47 matching lines @@
   // TODO(wala): Determine the best lowering sequences for each type.
   bool CanUsePextr =
       Ty == IceType_v8i16 || Ty == IceType_v8i1 || InstructionSet >= SSE4_1;
   if (CanUsePextr && Ty != IceType_v4f32) {
     // Use pextrb, pextrw, or pextrd.
     Constant *Mask = Ctx->getConstantInt32(Index);
     Variable *SourceVectR = legalizeToVar(SourceVectNotLegalized);
     _pextr(ExtractedElementR, SourceVectR, Mask);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use pshufd and movd/movss.
-    Variable *T = NULL;
+    Variable *T = nullptr;
     if (Index) {
       // The shuffle only needs to occur if the element to be extracted
       // is not at the lowest index.
       Constant *Mask = Ctx->getConstantInt32(Index);
       T = makeReg(Ty);
       _pshufd(T, legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem), Mask);
     } else {
       T = legalizeToVar(SourceVectNotLegalized);
     }
 
@@ skipping 48 matching lines @@
     InstFcmp::FCond Condition = Inst->getCondition();
     size_t Index = static_cast<size_t>(Condition);
     assert(Index < TableFcmpSize);
 
     if (TableFcmp[Index].SwapVectorOperands) {
       Operand *T = Src0;
       Src0 = Src1;
       Src1 = T;
     }
 
-    Variable *T = NULL;
+    Variable *T = nullptr;
 
     if (Condition == InstFcmp::True) {
       // makeVectorOfOnes() requires an integer vector type.
       T = makeVectorOfMinusOnes(IceType_v4i32);
     } else if (Condition == InstFcmp::False) {
       T = makeVectorOfZeros(Dest->getType());
     } else {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
 
@@ skipping 48 matching lines @@
   if (TableFcmp[Index].SwapScalarOperands) {
     Operand *Tmp = Src0;
     Src0 = Src1;
     Src1 = Tmp;
   }
   bool HasC1 = (TableFcmp[Index].C1 != CondX86::Br_None);
   bool HasC2 = (TableFcmp[Index].C2 != CondX86::Br_None);
   if (HasC1) {
     Src0 = legalize(Src0);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
-    Variable *T = NULL;
+    Variable *T = nullptr;
     _mov(T, Src0);
     _ucomiss(T, Src1RM);
   }
   Constant *Default = Ctx->getConstantInt32(TableFcmp[Index].Default);
   _mov(Dest, Default);
   if (HasC1) {
     InstX8632Label *Label = InstX8632Label::create(Func, this);
     _br(TableFcmp[Index].C1, Label);
     if (HasC2) {
       _br(TableFcmp[Index].C2, Label);
@@ skipping 216 matching lines @@
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
     Variable *T = makeReg(Ty);
     _movp(T, SourceVectRM);
     if (Ty == IceType_v4f32)
       _insertps(T, ElementRM, Ctx->getConstantInt32(Index << 4));
     else
       _pinsr(T, ElementRM, Ctx->getConstantInt32(Index));
     _movp(Inst->getDest(), T);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use shufps or movss.
-    Variable *ElementR = NULL;
+    Variable *ElementR = nullptr;
     Operand *SourceVectRM =
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
 
     if (InVectorElementTy == IceType_f32) {
       // ElementR will be in an XMM register since it is floating point.
       ElementR = legalizeToVar(ElementToInsertNotLegalized);
     } else {
       // Copy an integer to an XMM register.
       Operand *T = legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
       ElementR = makeReg(Ty);
@@ skipping 226 matching lines @@
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
     } else if (Val->getType() == IceType_i32) {
       Variable *T = legalizeToVar(Val);
       _bswap(T);
       _mov(Dest, T);
     } else {
       assert(Val->getType() == IceType_i16);
       Val = legalize(Val);
       Constant *Eight = Ctx->getConstantInt16(8);
-      Variable *T = NULL;
+      Variable *T = nullptr;
       _mov(T, Val);
       _rol(T, Eight);
       _mov(Dest, T);
     }
     return;
   }
   case Intrinsics::Ctpop: {
     Variable *Dest = Instr->getDest();
     Operand *Val = Instr->getArg(0);
     InstCall *Call =
@@ skipping 12 matching lines @@
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       _mov(DestHi, Zero);
     }
     return;
   }
   case Intrinsics::Ctlz: {
     // The "is zero undef" parameter is ignored and we always return
     // a well-defined value.
     Operand *Val = legalize(Instr->getArg(0));
     Operand *FirstVal;
-    Operand *SecondVal = NULL;
+    Operand *SecondVal = nullptr;
     if (Val->getType() == IceType_i64) {
       FirstVal = loOperand(Val);
       SecondVal = hiOperand(Val);
     } else {
       FirstVal = Val;
     }
     const bool IsCttz = false;
     lowerCountZeros(IsCttz, Val->getType(), Instr->getDest(), FirstVal,
                     SecondVal);
     return;
   }
   case Intrinsics::Cttz: {
     // The "is zero undef" parameter is ignored and we always return
     // a well-defined value.
     Operand *Val = legalize(Instr->getArg(0));
     Operand *FirstVal;
-    Operand *SecondVal = NULL;
+    Operand *SecondVal = nullptr;
     if (Val->getType() == IceType_i64) {
       FirstVal = hiOperand(Val);
       SecondVal = loOperand(Val);
     } else {
       FirstVal = Val;
     }
     const bool IsCttz = true;
     lowerCountZeros(IsCttz, Val->getType(), Instr->getDest(), FirstVal,
                     SecondVal);
     return;
   }
   case Intrinsics::Longjmp: {
-    InstCall *Call = makeHelperCall("longjmp", NULL, 2);
+    InstCall *Call = makeHelperCall("longjmp", nullptr, 2);
     Call->addArg(Instr->getArg(0));
     Call->addArg(Instr->getArg(1));
     lowerCall(Call);
     return;
   }
   case Intrinsics::Memcpy: {
     // In the future, we could potentially emit an inline memcpy/memset, etc.
     // for intrinsic calls w/ a known length.
-    InstCall *Call = makeHelperCall("memcpy", NULL, 3);
+    InstCall *Call = makeHelperCall("memcpy", nullptr, 3);
     Call->addArg(Instr->getArg(0));
     Call->addArg(Instr->getArg(1));
     Call->addArg(Instr->getArg(2));
     lowerCall(Call);
     return;
   }
   case Intrinsics::Memmove: {
-    InstCall *Call = makeHelperCall("memmove", NULL, 3);
+    InstCall *Call = makeHelperCall("memmove", nullptr, 3);
     Call->addArg(Instr->getArg(0));
     Call->addArg(Instr->getArg(1));
     Call->addArg(Instr->getArg(2));
     lowerCall(Call);
     return;
   }
   case Intrinsics::Memset: {
     // The value operand needs to be extended to a stack slot size
     // because the PNaCl ABI requires arguments to be at least 32 bits
     // wide.
     Operand *ValOp = Instr->getArg(1);
     assert(ValOp->getType() == IceType_i8);
     Variable *ValExt = Func->makeVariable(stackSlotType());
     lowerCast(InstCast::create(Func, InstCast::Zext, ValExt, ValOp));
-    InstCall *Call = makeHelperCall("memset", NULL, 3);
+    InstCall *Call = makeHelperCall("memset", nullptr, 3);
     Call->addArg(Instr->getArg(0));
     Call->addArg(ValExt);
     Call->addArg(Instr->getArg(2));
     lowerCall(Call);
     return;
   }
   case Intrinsics::NaClReadTP: {
     if (Ctx->getFlags().UseSandboxing) {
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
-      Operand *Src = OperandX8632Mem::create(
-          Func, IceType_i32, NULL, Zero, NULL, 0, OperandX8632Mem::SegReg_GS);
+      Operand *Src =
+          OperandX8632Mem::create(Func, IceType_i32, nullptr, Zero, nullptr, 0,
+                                  OperandX8632Mem::SegReg_GS);
       Variable *Dest = Instr->getDest();
-      Variable *T = NULL;
+      Variable *T = nullptr;
       _mov(T, Src);
       _mov(Dest, T);
     } else {
       InstCall *Call = makeHelperCall("__nacl_read_tp", Instr->getDest(), 0);
       lowerCall(Call);
     }
     return;
   }
   case Intrinsics::Setjmp: {
     InstCall *Call = makeHelperCall("setjmp", Instr->getDest(), 1);
@@ skipping 130 matching lines @@
         return true;
       }
     }
   }
   return false;
 }
 
 void TargetX8632::lowerAtomicRMW(Variable *Dest, uint32_t Operation,
                                  Operand *Ptr, Operand *Val) {
   bool NeedsCmpxchg = false;
-  LowerBinOp Op_Lo = NULL;
-  LowerBinOp Op_Hi = NULL;
+  LowerBinOp Op_Lo = nullptr;
+  LowerBinOp Op_Hi = nullptr;
   switch (Operation) {
   default:
     Func->setError("Unknown AtomicRMW operation");
     return;
   case Intrinsics::AtomicAdd: {
     if (Dest->getType() == IceType_i64) {
       // All the fall-through paths must set this to true, but use this
       // for asserting.
       NeedsCmpxchg = true;
       Op_Lo = &TargetX8632::_add;
       Op_Hi = &TargetX8632::_adc;
       break;
     }
     OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Dest->getType());
     const bool Locked = true;
-    Variable *T = NULL;
+    Variable *T = nullptr;
     _mov(T, Val);
     _xadd(Addr, T, Locked);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::AtomicSub: {
     if (Dest->getType() == IceType_i64) {
       NeedsCmpxchg = true;
       Op_Lo = &TargetX8632::_sub;
       Op_Hi = &TargetX8632::_sbb;
       break;
     }
     OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Dest->getType());
     const bool Locked = true;
-    Variable *T = NULL;
+    Variable *T = nullptr;
     _mov(T, Val);
     _neg(T);
     _xadd(Addr, T, Locked);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::AtomicOr:
     // TODO(jvoung): If Dest is null or dead, then some of these
     // operations do not need an "exchange", but just a locked op.
     // That appears to be "worth" it for sub, or, and, and xor.
@@ skipping 11 matching lines @@
   case Intrinsics::AtomicXor:
     NeedsCmpxchg = true;
     Op_Lo = &TargetX8632::_xor;
     Op_Hi = &TargetX8632::_xor;
     break;
   case Intrinsics::AtomicExchange:
     if (Dest->getType() == IceType_i64) {
       NeedsCmpxchg = true;
       // NeedsCmpxchg, but no real Op_Lo/Op_Hi need to be done. The values
       // just need to be moved to the ecx and ebx registers.
-      Op_Lo = NULL;
-      Op_Hi = NULL;
+      Op_Lo = nullptr;
+      Op_Hi = nullptr;
       break;
     }
     OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Dest->getType());
-    Variable *T = NULL;
+    Variable *T = nullptr;
     _mov(T, Val);
     _xchg(Addr, T);
     _mov(Dest, T);
     return;
   }
   // Otherwise, we need a cmpxchg loop.
   (void)NeedsCmpxchg;
   assert(NeedsCmpxchg);
   expandAtomicRMWAsCmpxchg(Op_Lo, Op_Hi, Dest, Ptr, Val);
 }
@@ skipping 17 matching lines @@
   //
   // For 32-bit:
   //   mov     eax, [ptr]
   // .LABEL:
   //   mov     <reg>, eax
   //   op      <reg>, [desired_adj]
   //   lock cmpxchg [ptr], <reg>
   //   jne     .LABEL
   //   mov     <dest>, eax
   //
-  // If Op_{Lo,Hi} are NULL, then just copy the value.
+  // If Op_{Lo,Hi} are nullptr, then just copy the value.
   Val = legalize(Val);
   Type Ty = Val->getType();
   if (Ty == IceType_i64) {
     Variable *T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
     Variable *T_eax = makeReg(IceType_i32, RegX8632::Reg_eax);
     OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Ty);
     _mov(T_eax, loOperand(Addr));
     _mov(T_edx, hiOperand(Addr));
     Variable *T_ecx = makeReg(IceType_i32, RegX8632::Reg_ecx);
     Variable *T_ebx = makeReg(IceType_i32, RegX8632::Reg_ebx);
     InstX8632Label *Label = InstX8632Label::create(Func, this);
-    const bool IsXchg8b = Op_Lo == NULL && Op_Hi == NULL;
+    const bool IsXchg8b = Op_Lo == nullptr && Op_Hi == nullptr;
     if (!IsXchg8b) {
       Context.insert(Label);
       _mov(T_ebx, T_eax);
       (this->*Op_Lo)(T_ebx, loOperand(Val));
       _mov(T_ecx, T_edx);
       (this->*Op_Hi)(T_ecx, hiOperand(Val));
     } else {
       // This is for xchg, which doesn't need an actual Op_Lo/Op_Hi.
       // It just needs the Val loaded into ebx and ecx.
       // That can also be done before the loop.
@@ skipping 25 matching lines @@
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Ty);
   Variable *T_eax = makeReg(Ty, RegX8632::Reg_eax);
   _mov(T_eax, Addr);
   InstX8632Label *Label = InstX8632Label::create(Func, this);
   Context.insert(Label);
   // We want to pick a different register for T than Eax, so don't use
-  // _mov(T == NULL, T_eax).
+  // _mov(T == nullptr, T_eax).
   Variable *T = makeReg(Ty);
   _mov(T, T_eax);
   (this->*Op_Lo)(T, Val);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, T, Locked);
   _br(CondX86::Br_ne, Label);
   // If Val is a variable, model the extended live range of Val through
   // the end of the loop, since it will be re-used by the loop.
   if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
     Context.insert(InstFakeUse::create(Func, ValVar));
@@ skipping 109 matching lines @@
     Index->dump(Func);
   else
     Str << "<null>";
   Str << ", Shift=" << Shift << ", Offset=" << Offset << "\n";
 }
 
 bool matchTransitiveAssign(const VariablesMetadata *VMetadata, Variable *&Var,
                            const Inst *&Reason) {
   // Var originates from Var=SrcVar ==>
   //   set Var:=SrcVar
-  if (Var == NULL)
+  if (Var == nullptr)
     return false;
   if (const Inst *VarAssign = VMetadata->getSingleDefinition(Var)) {
     assert(!VMetadata->isMultiDef(Var));
     if (llvm::isa<InstAssign>(VarAssign)) {
       Operand *SrcOp = VarAssign->getSrc(0);
       assert(SrcOp);
       if (Variable *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) {
         if (!VMetadata->isMultiDef(SrcVar) &&
             // TODO: ensure SrcVar stays single-BB
             true) {
           Var = SrcVar;
           Reason = VarAssign;
           return true;
         }
       }
     }
   }
   return false;
 }
 
 bool matchCombinedBaseIndex(const VariablesMetadata *VMetadata, Variable *&Base,
                             Variable *&Index, uint16_t &Shift,
                             const Inst *&Reason) {
-  // Index==NULL && Base is Base=Var1+Var2 ==>
+  // Index==nullptr && Base is Base=Var1+Var2 ==>
   //   set Base=Var1, Index=Var2, Shift=0
-  if (Base == NULL)
+  if (Base == nullptr)
     return false;
-  if (Index != NULL)
+  if (Index != nullptr)
     return false;
   const Inst *BaseInst = VMetadata->getSingleDefinition(Base);
-  if (BaseInst == NULL)
+  if (BaseInst == nullptr)
     return false;
   assert(!VMetadata->isMultiDef(Base));
   if (BaseInst->getSrcSize() < 2)
     return false;
   if (Variable *Var1 = llvm::dyn_cast<Variable>(BaseInst->getSrc(0))) {
     if (VMetadata->isMultiDef(Var1))
       return false;
     if (Variable *Var2 = llvm::dyn_cast<Variable>(BaseInst->getSrc(1))) {
       if (VMetadata->isMultiDef(Var2))
         return false;
       if (isAdd(BaseInst) &&
           // TODO: ensure Var1 and Var2 stay single-BB
           true) {
         Base = Var1;
         Index = Var2;
         Shift = 0; // should already have been 0
         Reason = BaseInst;
         return true;
       }
     }
   }
   return false;
 }
 
 bool matchShiftedIndex(const VariablesMetadata *VMetadata, Variable *&Index,
                        uint16_t &Shift, const Inst *&Reason) {
   // Index is Index=Var*Const && log2(Const)+Shift<=3 ==>
   //   Index=Var, Shift+=log2(Const)
-  if (Index == NULL)
+  if (Index == nullptr)
     return false;
   const Inst *IndexInst = VMetadata->getSingleDefinition(Index);
-  if (IndexInst == NULL)
+  if (IndexInst == nullptr)
     return false;
   assert(!VMetadata->isMultiDef(Index));
   if (IndexInst->getSrcSize() < 2)
     return false;
   if (const InstArithmetic *ArithInst =
           llvm::dyn_cast<InstArithmetic>(IndexInst)) {
     if (Variable *Var = llvm::dyn_cast<Variable>(ArithInst->getSrc(0))) {
       if (ConstantInteger32 *Const =
               llvm::dyn_cast<ConstantInteger32>(ArithInst->getSrc(1))) {
         if (ArithInst->getOp() == InstArithmetic::Mul &&
@@ skipping 28 matching lines @@
   }
   return false;
 }
 
 bool matchOffsetBase(const VariablesMetadata *VMetadata, Variable *&Base,
                      int32_t &Offset, const Inst *&Reason) {
   // Base is Base=Var+Const || Base is Base=Const+Var ==>
   //   set Base=Var, Offset+=Const
   // Base is Base=Var-Const ==>
   //   set Base=Var, Offset-=Const
-  if (Base == NULL)
+  if (Base == nullptr)
     return false;
   const Inst *BaseInst = VMetadata->getSingleDefinition(Base);
-  if (BaseInst == NULL)
+  if (BaseInst == nullptr)
     return false;
   assert(!VMetadata->isMultiDef(Base));
   if (const InstArithmetic *ArithInst =
           llvm::dyn_cast<const InstArithmetic>(BaseInst)) {
     if (ArithInst->getOp() != InstArithmetic::Add &&
         ArithInst->getOp() != InstArithmetic::Sub)
       return false;
     bool IsAdd = ArithInst->getOp() == InstArithmetic::Add;
-    Variable *Var = NULL;
-    ConstantInteger32 *Const = NULL;
+    Variable *Var = nullptr;
+    ConstantInteger32 *Const = nullptr;
     if (Variable *VariableOperand =
             llvm::dyn_cast<Variable>(ArithInst->getSrc(0))) {
       Var = VariableOperand;
       Const = llvm::dyn_cast<ConstantInteger32>(ArithInst->getSrc(1));
     } else if (IsAdd) {
       Const = llvm::dyn_cast<ConstantInteger32>(ArithInst->getSrc(0));
       Var = llvm::dyn_cast<Variable>(ArithInst->getSrc(1));
     }
-    if (Var == NULL || Const == NULL || VMetadata->isMultiDef(Var))
+    if (Var == nullptr || Const == nullptr || VMetadata->isMultiDef(Var))
       return false;
     int32_t MoreOffset = IsAdd ? Const->getValue() : -Const->getValue();
     if (Utils::WouldOverflowAdd(Offset, MoreOffset))
       return false;
     Base = Var;
     Offset += MoreOffset;
     Reason = BaseInst;
     return true;
   }
   return false;
 }
 
 void computeAddressOpt(Cfg *Func, const Inst *Instr, Variable *&Base,
                        Variable *&Index, uint16_t &Shift, int32_t &Offset) {
   Func->resetCurrentNode();
   if (Func->getContext()->isVerbose(IceV_AddrOpt)) {
     Ostream &Str = Func->getContext()->getStrDump();
     Str << "\nStarting computeAddressOpt for instruction:\n  ";
     Instr->dumpDecorated(Func);
   }
   (void)Offset; // TODO: pattern-match for non-zero offsets.
-  if (Base == NULL)
+  if (Base == nullptr)
     return;
   // If the Base has more than one use or is live across multiple
   // blocks, then don't go further.  Alternatively (?), never consider
   // a transformation that would change a variable that is currently
   // *not* live across basic block boundaries into one that *is*.
   if (Func->getVMetadata()->isMultiBlock(Base) /* || Base->getUseCount() > 1*/)
     return;
 
   const VariablesMetadata *VMetadata = Func->getVMetadata();
   bool Continue = true;
   while (Continue) {
-    const Inst *Reason = NULL;
+    const Inst *Reason = nullptr;
     if (matchTransitiveAssign(VMetadata, Base, Reason) ||
         matchTransitiveAssign(VMetadata, Index, Reason) ||
         matchCombinedBaseIndex(VMetadata, Base, Index, Shift, Reason) ||
         matchShiftedIndex(VMetadata, Index, Shift, Reason) ||
         matchOffsetBase(VMetadata, Base, Offset, Reason)) {
       dumpAddressOpt(Func, Base, Index, Shift, Offset, Reason);
     } else {
       Continue = false;
     }
 
@@ skipping 40 matching lines @@
   // TODO: Clean up and test thoroughly.
   // (E.g., if there is an mfence-all make sure the load ends up on the
   // same side of the fence).
   //
   // TODO: Why limit to Arithmetic instructions?  This could probably be
   // applied to most any instruction type.  Look at all source operands
   // in the following instruction, and if there is one instance of the
   // load instruction's dest variable, and that instruction ends that
   // variable's live range, then make the substitution.  Deal with
   // commutativity optimization in the arithmetic instruction lowering.
-  InstArithmetic *NewArith = NULL;
+  InstArithmetic *NewArith = nullptr;
   if (InstArithmetic *Arith =
           llvm::dyn_cast_or_null<InstArithmetic>(Context.getNextInst())) {
     Variable *DestLoad = Inst->getDest();
     Variable *Src0Arith = llvm::dyn_cast<Variable>(Arith->getSrc(0));
     Variable *Src1Arith = llvm::dyn_cast<Variable>(Arith->getSrc(1));
     if (Src1Arith == DestLoad && Arith->isLastUse(Src1Arith) &&
         DestLoad != Src0Arith) {
       NewArith = InstArithmetic::create(Func, Arith->getOp(), Arith->getDest(),
                                         Arith->getSrc(0), Src0);
     } else if (Src0Arith == DestLoad && Arith->isCommutative() &&
@@ skipping 10 matching lines @@
   }
 
   InstAssign *Assign = InstAssign::create(Func, Inst->getDest(), Src0);
   lowerAssign(Assign);
 }
 
 void TargetX8632::doAddressOptLoad() {
   Inst *Inst = Context.getCur();
   Variable *Dest = Inst->getDest();
   Operand *Addr = Inst->getSrc(0);
-  Variable *Index = NULL;
+  Variable *Index = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0; // TODO: make Constant
   // Vanilla ICE load instructions should not use the segment registers,
   // and computeAddressOpt only works at the level of Variables and Constants,
   // not other OperandX8632Mem, so there should be no mention of segment
   // registers there either.
   const OperandX8632Mem::SegmentRegisters SegmentReg =
       OperandX8632Mem::DefaultSegment;
   Variable *Base = llvm::dyn_cast<Variable>(Addr);
   computeAddressOpt(Func, Inst, Base, Index, Shift, Offset);
@@ skipping 11 matching lines @@
   if (RNG.getTrueWithProbability(Probability)) {
     _nop(RNG(X86_NUM_NOP_VARIANTS));
   }
 }
 
 void TargetX8632::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetX8632::lowerRet(const InstRet *Inst) {
-  Variable *Reg = NULL;
+  Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (Src0->getType() == IceType_i64) {
       Variable *eax = legalizeToVar(loOperand(Src0), RegX8632::Reg_eax);
       Variable *edx = legalizeToVar(hiOperand(Src0), RegX8632::Reg_edx);
       Reg = eax;
       Context.insert(InstFakeUse::create(Func, edx));
     } else if (isScalarFloatingType(Src0->getType())) {
       _fld(Src0);
     } else if (isVectorType(Src0->getType())) {
@@ skipping 125 matching lines @@
   } else {
     Value = legalize(Value, Legal_Reg | Legal_Imm);
     _store(Value, NewAddr);
   }
 }
 
 void TargetX8632::doAddressOptStore() {
   InstStore *Inst = llvm::cast<InstStore>(Context.getCur());
   Operand *Data = Inst->getData();
   Operand *Addr = Inst->getAddr();
-  Variable *Index = NULL;
+  Variable *Index = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0; // TODO: make Constant
   Variable *Base = llvm::dyn_cast<Variable>(Addr);
   // Vanilla ICE store instructions should not use the segment registers,
   // and computeAddressOpt only works at the level of Variables and Constants,
   // not other OperandX8632Mem, so there should be no mention of segment
   // registers there either.
   const OperandX8632Mem::SegmentRegisters SegmentReg =
       OperandX8632Mem::DefaultSegment;
   computeAddressOpt(Func, Inst, Base, Index, Shift, Offset);
@@ skipping 98 matching lines @@
       NextCast->setDeleted();
       _movp(NextCast->getDest(), legalizeToVar(SignExtendedResult));
       // Skip over the instruction.
       Context.advanceNext();
     }
   }
 }
 
 void TargetX8632::lowerUnreachable(const InstUnreachable * /*Inst*/) {
   const SizeT MaxSrcs = 0;
-  Variable *Dest = NULL;
+  Variable *Dest = nullptr;
   InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs);
   lowerCall(Call);
 }
 
 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to
 // preserve integrity of liveness analysis.  Undef values are also
 // turned into zeroes, since loOperand() and hiOperand() don't expect
 // Undef input.
 void TargetX8632::prelowerPhis() {
   CfgNode *Node = Context.getNode();
@@ skipping 94 matching lines @@
     Variable *SrcVar = llvm::dyn_cast<Variable>(Src);
     // Use normal assignment lowering, except lower mem=mem specially
     // so we can register-allocate at the same time.
     if (!isMemoryOperand(Dest) || !isMemoryOperand(Src)) {
       lowerAssign(Assign);
     } else {
       assert(Dest->getType() == Src->getType());
       const llvm::SmallBitVector &RegsForType =
           getRegisterSetForType(Dest->getType());
       llvm::SmallBitVector AvailRegsForType = RegsForType & Available;
-      Variable *SpillLoc = NULL;
-      Variable *Preg = NULL;
+      Variable *SpillLoc = nullptr;
+      Variable *Preg = nullptr;
       // TODO(stichnot): Opportunity for register randomization.
       int32_t RegNum = AvailRegsForType.find_first();
       bool IsVector = isVectorType(Dest->getType());
       bool NeedSpill = (RegNum == -1);
       if (NeedSpill) {
         // Pick some register to spill and update RegNum.
         // TODO(stichnot): Opportunity for register randomization.
         RegNum = RegsForType.find_first();
         Preg = getPhysicalRegister(RegNum, Dest->getType());
         SpillLoc = Func->makeVariable(Dest->getType());
@@ skipping 128 matching lines @@
   // If we're asking for a specific physical register, make sure we're
   // not allowing any other operand kinds.  (This could be future
   // work, e.g. allow the shl shift amount to be either an immediate
   // or in ecx.)
   assert(RegNum == Variable::NoRegister || Allowed == Legal_Reg);
   if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(From)) {
     // Before doing anything with a Mem operand, we need to ensure
     // that the Base and Index components are in physical registers.
     Variable *Base = Mem->getBase();
     Variable *Index = Mem->getIndex();
-    Variable *RegBase = NULL;
-    Variable *RegIndex = NULL;
+    Variable *RegBase = nullptr;
+    Variable *RegIndex = nullptr;
     if (Base) {
       RegBase = legalizeToVar(Base);
     }
     if (Index) {
       RegIndex = legalizeToVar(Index);
     }
     if (Base != RegBase || Index != RegIndex) {
       From = OperandX8632Mem::create(
           Func, Mem->getType(), RegBase, Mem->getOffset(), RegIndex,
           Mem->getShift(), Mem->getSegmentRegister());
@@ skipping 295 matching lines @@
   } else if (IsConstant || IsExternal)
     Str << "\t.zero\t" << Size << "\n";
   // Size is part of .comm.
 
   if (IsConstant || HasNonzeroInitializer || IsExternal)
     Str << "\t.size\t" << MangledName << ", " << Size << "\n";
   // Size is part of .comm.
 }
 
 } // end of namespace Ice