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Side by Side Diff: source/libvpx/vp9/encoder/x86/vp9_subpel_variance.asm

Issue 812033011: libvpx: Pull from upstream (Closed) Base URL: svn://svn.chromium.org/chrome/trunk/deps/third_party/libvpx/
Patch Set: Created 5 years, 11 months ago
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1 ; 1 ;
2 ; Copyright (c) 2010 The WebM project authors. All Rights Reserved. 2 ; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
3 ; 3 ;
4 ; Use of this source code is governed by a BSD-style license 4 ; Use of this source code is governed by a BSD-style license
5 ; that can be found in the LICENSE file in the root of the source 5 ; that can be found in the LICENSE file in the root of the source
6 ; tree. An additional intellectual property rights grant can be found 6 ; tree. An additional intellectual property rights grant can be found
7 ; in the file PATENTS. All contributing project authors may 7 ; in the file PATENTS. All contributing project authors may
8 ; be found in the AUTHORS file in the root of the source tree. 8 ; be found in the AUTHORS file in the root of the source tree.
9 ; 9 ;
10 10
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94 paddd m7, m3 94 paddd m7, m3
95 paddd m6, m4 95 paddd m6, m4
96 pshufd m3, m7, 0x1 96 pshufd m3, m7, 0x1
97 movhlps m4, m6 97 movhlps m4, m6
98 paddd m7, m3 98 paddd m7, m3
99 paddd m6, m4 99 paddd m6, m4
100 mov r1, ssem ; r1 = unsigned int *sse 100 mov r1, ssem ; r1 = unsigned int *sse
101 pshufd m4, m6, 0x1 101 pshufd m4, m6, 0x1
102 movd [r1], m7 ; store sse 102 movd [r1], m7 ; store sse
103 paddd m6, m4 103 paddd m6, m4
104 movd rax, m6 ; store sum as return value 104 movd raxd, m6 ; store sum as return value
105 %else ; mmsize == 8 105 %else ; mmsize == 8
106 pshufw m4, m6, 0xe 106 pshufw m4, m6, 0xe
107 pshufw m3, m7, 0xe 107 pshufw m3, m7, 0xe
108 paddw m6, m4 108 paddw m6, m4
109 paddd m7, m3 109 paddd m7, m3
110 pcmpgtw m5, m6 ; mask for 0 > x 110 pcmpgtw m5, m6 ; mask for 0 > x
111 mov r1, ssem ; r1 = unsigned int *sse 111 mov r1, ssem ; r1 = unsigned int *sse
112 punpcklwd m6, m5 ; sign-extend m6 word->dword 112 punpcklwd m6, m5 ; sign-extend m6 word->dword
113 movd [r1], m7 ; store sse 113 movd [r1], m7 ; store sse
114 pshufw m4, m6, 0xe 114 pshufw m4, m6, 0xe
115 paddd m6, m4 115 paddd m6, m4
116 movd rax, m6 ; store sum as return value 116 movd raxd, m6 ; store sum as return value
117 %endif 117 %endif
118 RET 118 RET
119 %endmacro 119 %endmacro
120 120
121 %macro INC_SRC_BY_SRC_STRIDE 0 121 %macro INC_SRC_BY_SRC_STRIDE 0
122 %if ARCH_X86=1 && CONFIG_PIC=1 122 %if ARCH_X86=1 && CONFIG_PIC=1
123 add srcq, src_stridemp 123 add srcq, src_stridemp
124 %else 124 %else
125 add srcq, src_strideq 125 add srcq, src_strideq
126 %endif 126 %endif
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1411 SUBPEL_VARIANCE 4, 1 1411 SUBPEL_VARIANCE 4, 1
1412 INIT_XMM sse2 1412 INIT_XMM sse2
1413 SUBPEL_VARIANCE 8, 1 1413 SUBPEL_VARIANCE 8, 1
1414 SUBPEL_VARIANCE 16, 1 1414 SUBPEL_VARIANCE 16, 1
1415 1415
1416 INIT_MMX ssse3 1416 INIT_MMX ssse3
1417 SUBPEL_VARIANCE 4, 1 1417 SUBPEL_VARIANCE 4, 1
1418 INIT_XMM ssse3 1418 INIT_XMM ssse3
1419 SUBPEL_VARIANCE 8, 1 1419 SUBPEL_VARIANCE 8, 1
1420 SUBPEL_VARIANCE 16, 1 1420 SUBPEL_VARIANCE 16, 1
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