Shorter opcodes in ia32 in some cases where register is wrapped in an operand.

src/ia32/assembler-ia32.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 439 matching lines @@
 }
 
 
 void Assembler::push(Register src) {
   EnsureSpace ensure_space(this);
   EMIT(0x50 | src.code());
 }
 
 
 void Assembler::push(const Operand& src) {
+  if (src.is_reg_only()) {
+    push(src.reg());
+    return;
+  }
   EnsureSpace ensure_space(this);
   EMIT(0xFF);
   emit_operand(esi, src);
 }
 
 
 void Assembler::push(Handle<Object> handle) {
   EnsureSpace ensure_space(this);
   EMIT(0x68);
   emit(handle);
 }
 
 
 void Assembler::pop(Register dst) {
   ASSERT(reloc_info_writer.last_pc() != NULL);
   EnsureSpace ensure_space(this);
   EMIT(0x58 | dst.code());
 }
 
 
 void Assembler::pop(const Operand& dst) {
+  if (dst.is_reg_only()) {
+    pop(dst.reg());
+    return;
+  }
   EnsureSpace ensure_space(this);
   EMIT(0x8F);
   emit_operand(eax, dst);
 }
 
 
 void Assembler::enter(const Immediate& size) {
   EnsureSpace ensure_space(this);
   EMIT(0xC8);
   emit_w(size);
@@ skipping 62 matching lines @@
 
 
 void Assembler::mov(Register dst, Handle<Object> handle) {
   EnsureSpace ensure_space(this);
   EMIT(0xB8 | dst.code());
   emit(handle);
 }
 
 
 void Assembler::mov(Register dst, const Operand& src) {
+  if (src.is_reg_only()) {
+    mov(dst, src.reg());
+    return;
+  }
   EnsureSpace ensure_space(this);
   EMIT(0x8B);
   emit_operand(dst, src);
 }
 
 
 void Assembler::mov(Register dst, Register src) {
   EnsureSpace ensure_space(this);
   EMIT(0x89);
   EMIT(0xC0 | src.code() << 3 | dst.code());
@@ skipping 285 matching lines @@
 }
 
 
 void Assembler::dec(Register dst) {
   EnsureSpace ensure_space(this);
   EMIT(0x48 | dst.code());
 }
 
 
 void Assembler::dec(const Operand& dst) {
+  if (dst.is_reg_only()) {
+    dec(dst.reg());
+    return;
+  }
   EnsureSpace ensure_space(this);
   EMIT(0xFF);
   emit_operand(ecx, dst);
 }
 
 
 void Assembler::cdq() {
   EnsureSpace ensure_space(this);
   EMIT(0x99);
 }
@@ skipping 35 matching lines @@
 }
 
 
 void Assembler::inc(Register dst) {
   EnsureSpace ensure_space(this);
   EMIT(0x40 | dst.code());
 }
 
 
 void Assembler::inc(const Operand& dst) {
+  if (dst.is_reg_only()) {
+    inc(dst.reg());
+    return;
+  }
   EnsureSpace ensure_space(this);
   EMIT(0xFF);
   emit_operand(eax, dst);
 }
 
 
 void Assembler::lea(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   EMIT(0x8D);
   emit_operand(dst, src);
@@ skipping 1573 matching lines @@
     fprintf(coverage_log, "%s\n", file_line);
     fflush(coverage_log);
   }
 }
 
 #endif
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_IA32