Subzero: Randomize register assignment.

tests_lit/llvm2ice_tests/randomize-regalloc.ll

+; This is a smoke test of randomized register allocation.  The output
+; of this test will change with changes to the random number generator
+; implementation.
+
+; RUN: %p2i -i %s --args -O2 -sz-seed=1 -randomize-regalloc \
+; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
+; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN:   | FileCheck %s --check-prefix=CHECK
+; RUN: %p2i -i %s --args -Om1 -sz-seed=1 -randomize-regalloc \
+; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
+; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN:   | FileCheck %s --check-prefix=OPTM1

[JF, 2014/12/17 18:56:19]

Also test with another seed that 1.

[Jim Stichnoth, 2014/12/18 18:52:03]

Done.

+
+define <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
+entry:
+  %res = mul <4 x i32> %a, %b
+  ret <4 x i32> %res
+; OPTM1-LABEL: mul_v4i32:
+; OPTM1: sub     esp, 60
+; OPTM1-NEXT: movups  xmmword ptr [esp + 32], xmm0
+; OPTM1-NEXT: movups  xmmword ptr [esp + 16], xmm1
+; OPTM1-NEXT: movups  xmm0, xmmword ptr [esp + 32]
+; OPTM1-NEXT: pshufd  xmm7, xmmword ptr [esp + 32], 49
+; OPTM1-NEXT: pshufd  xmm4, xmmword ptr [esp + 16], 49
+; OPTM1-NEXT: pmuludq xmm0, xmmword ptr [esp + 16]
+; OPTM1-NEXT: pmuludq xmm7, xmm4
+; OPTM1-NEXT: shufps  xmm0, xmm7, -120
+; OPTM1-NEXT: pshufd  xmm0, xmm0, -40
+; OPTM1-NEXT: movups  xmmword ptr [esp], xmm0
+; OPTM1-NEXT: movups  xmm0, xmmword ptr [esp]
+; OPTM1-NEXT: add     esp, 60
+; OPTM1-NEXT: ret
+
+; CHECK-LABEL: mul_v4i32:
+; CHECK: movups  xmm6, xmm0
+; CHECK-NEXT: pshufd  xmm0, xmm0, 49
+; CHECK-NEXT: pshufd  xmm5, xmm1, 49
+; CHECK-NEXT: pmuludq xmm6, xmm1
+; CHECK-NEXT: pmuludq xmm0, xmm5
+; CHECK-NEXT: shufps  xmm6, xmm0, -120
+; CHECK-NEXT: pshufd  xmm6, xmm6, -40
+; CHECK-NEXT: movups  xmm0, xmm6
+; CHECK-NEXT: ret
+}
+
+; ERRORS-NOT: ICE translation error
+; DUMP-NOT: SZ